[clang] 51feb1a - [RISCV] Use 'int' for return type for clz_64/clo_64 tests in riscv64-xtheadbb.c. NFC

[Craig Topper via cfe-commits]

Author: Craig Topper
Date: 2023-07-06T00:25:20-07:00
New Revision: 51feb1a72c5beb8f46d2f5569f3c3398f8902272

URL: https://github.com/llvm/llvm-project/commit/51feb1a72c5beb8f46d2f5569f3c3398f8902272
DIFF: https://github.com/llvm/llvm-project/commit/51feb1a72c5beb8f46d2f5569f3c3398f8902272.diff

LOG: [RISCV] Use 'int' for return type for clz_64/clo_64 tests in riscv64-xtheadbb.c. NFC

This matches the definition for the underlying builtins and what
is done in the Zbb test.

Added: 
    

Modified: 
    clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c

Removed: 
    


################################################################################
diff  --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c
index 3b6ef569e6b85f..70b04a66334e62 100644
--- a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c
@@ -29,25 +29,31 @@ int clo_32(int a) {
 
 // RV64XTHEADBB-LABEL: @clz_64(
 // RV64XTHEADBB-NEXT:  entry:
+// RV64XTHEADBB-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 // RV64XTHEADBB-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
 // RV64XTHEADBB-NEXT:    store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
 // RV64XTHEADBB-NEXT:    [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
 // RV64XTHEADBB-NEXT:    [[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[TMP0]], i1 false)
-// RV64XTHEADBB-NEXT:    ret i64 [[TMP1]]
+// RV64XTHEADBB-NEXT:    store i64 [[TMP1]], ptr [[RETVAL]], align 4
+// RV64XTHEADBB-NEXT:    [[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 4
+// RV64XTHEADBB-NEXT:    ret i32 [[TMP2]]
 //
-long clz_64(long a) {
+int clz_64(long a) {
   return __builtin_riscv_clz_64(a);
 }
 
 // RV64XTHEADBB-LABEL: @clo_64(
 // RV64XTHEADBB-NEXT:  entry:
+// RV64XTHEADBB-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 // RV64XTHEADBB-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
 // RV64XTHEADBB-NEXT:    store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
 // RV64XTHEADBB-NEXT:    [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
 // RV64XTHEADBB-NEXT:    [[NOT:%.*]] = xor i64 [[TMP0]], -1
 // RV64XTHEADBB-NEXT:    [[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[NOT]], i1 false)
-// RV64XTHEADBB-NEXT:    ret i64 [[TMP1]]
+// RV64XTHEADBB-NEXT:    store i64 [[TMP1]], ptr [[RETVAL]], align 4
+// RV64XTHEADBB-NEXT:    [[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 4
+// RV64XTHEADBB-NEXT:    ret i32 [[TMP2]]
 //
-long clo_64(long a) {
+int clo_64(long a) {
   return __builtin_riscv_clz_64(~a);
 }