[PATCH] D153370: [RISCV] Add support for custom instructions for Sifive S76.

[garvit gupta via Phabricator via cfe-commits]

garvitgupta08 created this revision.
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Support for below instruction is added

1. CFLUSH.D.L1 <https://reviews.llvm.org/L1>
2. CDISCARD.D.L1 <https://reviews.llvm.org/L1>
3. CEASE

Additionally, Zihintpause extension is added to sifive s76 for pause
instruction.

Spec - https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D153370

Files:
  clang/test/Driver/riscv-cpus.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
  llvm/lib/Target/RISCV/RISCVProcessors.td
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/xsfcie-invalid.s
  llvm/test/MC/RISCV/xsfcie-valid.s

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