[PATCH] D147732: [AMDGPU] Add type mangling for {read, write, readfirst, perm}lane intrinsics

[Matt Arsenault via Phabricator via cfe-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp:209
+    bool is16Bit =
+        (EltType->isIntegerTy() && EltType->getIntegerBitWidth() == 16) ||
+        (EltType->isHalfTy());
----------------
isIntegerTy(16). Also, just check the bitsize is 16. Might as well also handle bfloat


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Comment at: llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp:301-310
+  if (Ty->isPointerTy()) {
+    unsigned BitWidth = DL->getTypeSizeInBits(Ty);
+    auto ResTy = Result->getType();
+    if (ResTy->isVectorTy()) {
+      auto Scalarized = B.CreateBitCast(
+          Result, IntegerType::get(Mod->getContext(), BitWidth));
+      return B.CreateIntToPtr(Scalarized, Ty);
----------------
Just let pointer types pass through to codegen, we try really hard to never introduce ptrtoint/inttoptr


================
Comment at: llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll:5
+declare i16 @llvm.amdgcn.readlane.i16(i16, i32) #0
+declare half @llvm.amdgcn.readlane.f16(half, i32) #0
+declare float @llvm.amdgcn.readlane.f32(float, i32) #0
----------------
Add bfloat and <2 x i16>, <2 x half>, <2 x bfloat> tests


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147732/new/

https://reviews.llvm.org/D147732