[PATCH] D150926: [RISCV] Support LMUL!=1 for __attribute__((riscv_rvv_vector_bits(N)))

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.


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Comment at: clang/lib/Sema/SemaType.cpp:8338
   // The attribute vector size must match -mrvv-vector-bits.
-  if (VecSize != VScale->first * MinElts * EltSize) {
+  unsigned ExpectedSize = VScale->first * MinElts * EltSize;
+  if (VecSize != ExpectedSize) {
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aaron.ballman wrote:
> Random thought I didn't think to ask earlier: is it possible for this multiplication to overflow (if so, we should add test coverage to make sure we don't do bad things)?
The largest value for -mrvv-vector-bits is 65536 which makes VScale->first 65536/64 == 1024. MinElts and EltSize should be small enough that it won't overflow.

I'm not sure if there's any protection if someone bypasses the driver with `-Xclang -mvscale-min=` and uses a larger value.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150926/new/

https://reviews.llvm.org/D150926