[PATCH] D150926: [RISCV] Support LMUL!=1 for __attribute__((riscv_rvv_vector_bits(N)))

[Aaron Ballman via Phabricator via cfe-commits]

aaron.ballman added inline comments.


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Comment at: clang/include/clang/Basic/AttrDocs.td:2350
+
+``vbool*_t`` types are not supported at this time.
 }];
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Do you have test coverage that demonstrates this?


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Comment at: clang/lib/AST/Type.cpp:2437
     switch (BT->getKind()) {
     // FIXME: Support more than LMUL 1.
 #define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned, IsFP) \
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FIXME is now stale and can be removed?


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Comment at: clang/lib/Sema/SemaType.cpp:8338
   // The attribute vector size must match -mrvv-vector-bits.
-  if (VecSize != VScale->first * MinElts * EltSize) {
+  unsigned ExpectedSize = VScale->first * MinElts * EltSize;
+  if (VecSize != ExpectedSize) {
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Random thought I didn't think to ask earlier: is it possible for this multiplication to overflow (if so, we should add test coverage to make sure we don't do bad things)?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150926/new/

https://reviews.llvm.org/D150926