[PATCH] D150926: [RISCV] Support LMUL!=1 for __attribute__((riscv_rvv_vector_bits(N)))

[Craig Topper via Phabricator via cfe-commits]

craig.topper created this revision.
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The first patch supported only LMUL=1 types. This patch supports
LMUL!=1.

LMUL is length multiplier that allows multiple vector registers to
be treated as one large register or a fraction of a single vector
register. Supported values for LMUL are 1/8, 1/4, 1/2, 1, 2, 4, and 8.

An LMUL=2 type will be twice as large as an LMUL=1 type. An LMUL=1/2
type will be half the size as an LMUL=1 type.

Type name with "m2" is LMUL=2, "m4" is LMUL=4.
Type name with "mf2" is LMUL=1/2, "mf4" is LMUL=1/4.

For the LMUL!=1 types the user will need to scale __riscv_v_fixed_vlen
by the LMUL before passing to the attribute.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D150926

Files:
  clang/include/clang/Basic/AttrDocs.td
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/Type.cpp
  clang/lib/Sema/SemaType.cpp
  clang/test/CodeGen/attr-riscv-rvv-vector-bits-codegen.c
  clang/test/CodeGen/attr-riscv-rvv-vector-bits-types.c
  clang/test/Driver/riscv-rvv-vector-bits.c
  clang/test/Sema/attr-riscv-rvv-vector-bits.c

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