[PATCH] D149562: [clang-format] Stop comment disrupting indentation of Verilog ports

[Owen Pan via Phabricator via cfe-commits]

owenpan added a comment.

In D149562#4312573 <https://reviews.llvm.org/D149562#4312573>, @sstwcw wrote:

> The port list thing and the comment thing work fine for now, except
> when there is a comment for the first port.  The comment on the first
> line would cause the port list to be indented, like this:
>
>   module x
>       ( // first port
>           input x1,
>           // second port
>           input x2,
>           // third port
>           input x3,
>           // forth port
>           input x4);
>   endmodule
>
> After this patch, a comment on the first line would not cause the
> problem.  Now the code gets formatted like this.  The ports are
> indented the same whether or not there is a comment on the first line.
>
>   module x
>       (// first port
>        input x1,
>        // second port
>        input x2,
>        // third port
>        input x3,
>        // forth port
>        input x4);
>   endmodule

See https://github.com/llvm/llvm-project/issues/55487#issuecomment-1321355199, which may be relevant.


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