[PATCH] D149562: [clang-format] Stop comment disrupting indentation of Verilog ports

[sstwcw via Phabricator via cfe-commits]

sstwcw added a comment.

In D149562#4310396 <https://reviews.llvm.org/D149562#4310396>, @HazardyKnusperkeks wrote:

> I don't see the problem, could you elaborate a bit more? (Keep in mind, I have no idea about Verilog.)

The current way the port list gets formatted is like this:

  module x
      (input x1,
       input x2,
       input x3,
       input x4);
  endmodule

One may want to add a comment for one of the ports like this:

  module x
      (input x1,
       // second port
       input x2,
       // third port
       input x3,
       // forth port
       input x4);
  endmodule

The port list thing and the comment thing work fine for now, except
when there is a comment for the first port.  The comment on the first
line would cause the port list to be indented, like this:

  module x
      ( // first port
          input x1,
          // second port
          input x2,
          // third port
          input x3,
          // forth port
          input x4);
  endmodule

After this patch, a comment on the first line would not cause the
problem.  Now the code gets formatted like this.  The ports are
indented the same whether or not there is a comment on the first line.

  module x
      (// first port
       input x1,
       // second port
       input x2,
       // third port
       input x3,
       // forth port
       input x4);
  endmodule



================
Comment at: clang/include/clang/Format/Format.h:4027
+  /// is probably for the port on the following line instead of the parenthesis
+  /// it follows.
   /// \code
----------------
MyDeveloperDay wrote:
> This seems an odd corner case
See the last block of code in the example I added.  This is the only way I came up with to ensure that the comment for the first port is aligned with the comments for the rest of the ports and that whether the first comment exists does not affect how other lines are indented.


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