[PATCH] D145088: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.


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Comment at: clang/include/clang/AST/ASTContext.h:2262
+  /// Return true if the given vector types are lax-compatible RISC-V vector
+  /// types as defined by -flax-vector-conversions=, false otherwise.
+  bool areLaxCompatibleRVVTypes(QualType FirstType, QualType SecondType);
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erichkeane wrote:
> I still had to look this one up.
That's not quite the description of -flax-vector-conversion. The total vector size must be the same. But the element size and number of elements can be different.


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  https://reviews.llvm.org/D145088/new/

https://reviews.llvm.org/D145088