[PATCH] D145088: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.


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Comment at: clang/lib/Sema/SemaType.cpp:8234
+                                             ParsedAttr &Attr, Sema &S) {
+  // Target must have SVE.
+  if (!S.Context.getTargetInfo().hasFeature("zve32x")) {
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I need to fix this comment.


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Comment at: clang/lib/Sema/SemaType.cpp:8265
+  // The attribute vector size must match -mrvv-vector-bits.
+  // FIXME: LMUL from type and scale it.
+  if (VecSize != VScale->first * llvm::RISCV::RVVBitsPerBlock) {
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aaron.ballman wrote:
> Should this be done as part of this patch (are we accepting code we shouldn't be accepting)?
No. I need to phrase this FIXME better. I'm only accepting types that have LMUL=1. (length multiplier). This is enforced in `Type::isRVVVLSBuiltinType()` where there's another FIXME about LMUL=1.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145088/new/

https://reviews.llvm.org/D145088