[PATCH] D145088: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

[Aaron Ballman via Phabricator via cfe-commits]

aaron.ballman added reviewers: erichkeane, rjmccall, efriedma.
aaron.ballman added a comment.

Adding Erich as attributes code owner and John/Eli as ABI code owners.



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Comment at: clang/lib/Sema/SemaType.cpp:8265
+  // The attribute vector size must match -mrvv-vector-bits.
+  // FIXME: LMUL from type and scale it.
+  if (VecSize != VScale->first * llvm::RISCV::RVVBitsPerBlock) {
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Should this be done as part of this patch (are we accepting code we shouldn't be accepting)?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145088/new/

https://reviews.llvm.org/D145088