[PATCH] D146401: [clang-format] Don't squash Verilog escaped identifiers

[sstwcw via Phabricator via cfe-commits]

sstwcw marked an inline comment as done.
sstwcw added inline comments.


================
Comment at: clang/unittests/Format/FormatTestVerilog.cpp:897
 }
+} // namespace
+} // namespace test
----------------
MyDeveloperDay wrote:
> is this correct? do you have an anonymous namespace?
It is correct.  The class `FormatTestVerilog` is only used in this file.  Other files have it too.  I didn't notice it when I copied the first few lines from `FormatTest.cpp` this time, but I probably forgot to add it when creating the file.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146401/new/

https://reviews.llvm.org/D146401