[PATCH] D146401: [clang-format] Don't squash Verilog escaped identifiers

[MyDeveloperDay via Phabricator via cfe-commits]

MyDeveloperDay added inline comments.


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Comment at: clang/unittests/Format/FormatTestVerilog.cpp:897
 }
+} // namespace
+} // namespace test
----------------
is this correct? do you have an anonymous namespace?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146401/new/

https://reviews.llvm.org/D146401