[PATCH] D146401: [clang-format] Don't squash Verilog escaped identifiers
MyDeveloperDay via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Wed Mar 22 03:36:30 PDT 2023
MyDeveloperDay added inline comments.
================
Comment at: clang/unittests/Format/FormatTestVerilog.cpp:897
}
+} // namespace
+} // namespace test
----------------
is this correct? do you have an anonymous namespace?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D146401/new/
https://reviews.llvm.org/D146401
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