[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

[Slava Zakharin via Phabricator via cfe-commits]

vzakhari added inline comments.


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Comment at: flang/test/Driver/target-cpu-features.f90:1
-! REQUIRES: aarch64-registered-target, x86-registered-target
+! REQUIRES: aarch64-registered-target, x86-registered-target, riscv-registered-target
 
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Can we split this test so that people who do not build riscv target still have aarch64/x86 targets tested in their workspaces?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145883/new/

https://reviews.llvm.org/D145883