[PATCH] D145088: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added a comment.

In D145088#4165180 <https://reviews.llvm.org/D145088#4165180>, @tschuett wrote:

>   Any binary that uses this feature is not forward portable to hardware
>   with a larger vector size. That's true for SVE as well.
>
> I did not understood this sentence. AFAIK, SVE uses the ptrue instruction  to generate a mask to only activate the necessary lanes. If I do fixed length SVE with 128 bit and you give a machine 2048 bits, then it should still work. Probably I missed something.

Maybe I'm wrong, but there are few statements here https://developer.arm.com/documentation/101726/0400/Coding-for-Scalable-Vector-Extension--SVE-/SVE-Vector-Length-Specific--VLS--programming

"When you implement your code, you can choose to use fixed-length vectors. Fixed-length vectors enable the use of constructs that are generally not safe for code which is to be run on targets with unknown SVE vector lengths. However, if you do not require your code to be portable, VLS code can be more optimal than VLA code for a specific SVE implementation."

"Generated VLS code must only be executed on hardware which offers an SVE vector length compatible with the intent of the programmer. "


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