[PATCH] D145088: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

[Thorsten via Phabricator via cfe-commits]

tschuett added a comment.

  Any binary that uses this feature is not forward portable to hardware
  with a larger vector size. That's true for SVE as well.

I did not understood this sentence. AFAIK, SVE uses the ptrue instruction  to generate a mask to only activate the necessary lanes. If I do fixed length SVE with 128 bit and you give a machine 2048 bits, then it should still work. Probably I missed something.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145088/new/

https://reviews.llvm.org/D145088