[PATCH] D143825: [clang-format] Put ports on separate lines in Verilog module headers

[sstwcw via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG6e473aeffdc1: [clang-format] Put ports on separate lines in Verilog module headers (authored by sstwcw).

Changed prior to commit:
  https://reviews.llvm.org/D143825?vs=498376&id=498711#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143825/new/

https://reviews.llvm.org/D143825

Files:
  clang/lib/Format/FormatToken.h
  clang/lib/Format/TokenAnnotator.cpp
  clang/unittests/Format/FormatTestVerilog.cpp

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