[PATCH] D143825: [clang-format] Put ports on separate lines in Verilog module headers

[Owen Pan via Phabricator via cfe-commits]

owenpan added inline comments.


================
Comment at: clang/lib/Format/TokenAnnotator.cpp:2665
+    if (Style.isVerilog() && Precedence == prec::Comma &&
+        VerilogFirstOfType != nullptr) {
+      addFakeParenthesis(VerilogFirstOfType, prec::Comma);
----------------
sstwcw wrote:
> owenpan wrote:
> > And other places as well.
> @HazardyKnusperkeks Do you agree?  I remember you once said you preferred the `nullptr` style.
See D144355. Not using `nullptr` in conditionals was one of the first LLVM styles I had to get used to when I started contributing.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143825/new/

https://reviews.llvm.org/D143825