[clang] caf393d - Fix format for `case` in .proto files

[Krasimir Georgiev via cfe-commits]

Author: Matt Kulukundis
Date: 2023-01-16T17:43:50Z
New Revision: caf393da1823d50852f51604b3793e8f4a23c140

URL: https://github.com/llvm/llvm-project/commit/caf393da1823d50852f51604b3793e8f4a23c140
DIFF: https://github.com/llvm/llvm-project/commit/caf393da1823d50852f51604b3793e8f4a23c140.diff

LOG: Fix format for `case` in .proto files

Fix format for `case` in .proto files

Reviewed By: krasimir, echristo

Differential Revision: https://reviews.llvm.org/D141547

Added: 
    

Modified: 
    clang/lib/Format/UnwrappedLineParser.cpp
    clang/unittests/Format/FormatTestProto.cpp

Removed: 
    


################################################################################
diff  --git a/clang/lib/Format/UnwrappedLineParser.cpp b/clang/lib/Format/UnwrappedLineParser.cpp
index c97ecc7821209..effb0ecb368bb 100644
--- a/clang/lib/Format/UnwrappedLineParser.cpp
+++ b/clang/lib/Format/UnwrappedLineParser.cpp
@@ -590,8 +590,9 @@ bool UnwrappedLineParser::parseLevel(const FormatToken *OpeningBrace,
       [[fallthrough]];
     }
     case tok::kw_case:
-      if (Style.isVerilog() ||
+      if (Style.isProto() || Style.isVerilog() ||
           (Style.isJavaScript() && Line->MustBeDeclaration)) {
+        // Proto: there are no switch/case statements
         // Verilog: Case labels don't have this word. We handle case
         // labels including default in TokenAnnotator.
         // JavaScript: A 'case: string' style field declaration.
@@ -1620,7 +1621,11 @@ void UnwrappedLineParser::parseStructuralElement(
     // e.g. "default void f() {}" in a Java interface.
     break;
   case tok::kw_case:
-    // In Verilog switch is called case.
+    // Proto: there are no switch/case statements.
+    if (Style.isProto()) {
+      nextToken();
+      return;
+    }
     if (Style.isVerilog()) {
       parseBlock();
       addUnwrappedLine();
@@ -2100,6 +2105,11 @@ void UnwrappedLineParser::parseStructuralElement(
       parseNew();
       break;
     case tok::kw_case:
+      // Proto: there are no switch/case statements.
+      if (Style.isProto()) {
+        nextToken();
+        return;
+      }
       // In Verilog switch is called case.
       if (Style.isVerilog()) {
         parseBlock();

diff  --git a/clang/unittests/Format/FormatTestProto.cpp b/clang/unittests/Format/FormatTestProto.cpp
index 1ff7c22a6df78..5de40b6eae597 100644
--- a/clang/unittests/Format/FormatTestProto.cpp
+++ b/clang/unittests/Format/FormatTestProto.cpp
@@ -113,6 +113,13 @@ TEST_F(FormatTestProto, EnumAsFieldName) {
                "}");
 }
 
+TEST_F(FormatTestProto, CaseAsFieldName) {
+  verifyFormat("message SomeMessage {\n"
+               "  required string case = 1;\n"
+               "  repeated int32 fizz = 2;\n"
+               "}");
+}
+
 TEST_F(FormatTestProto, UnderstandsReturns) {
   verifyFormat("rpc Search(SearchRequest) returns (SearchResponse);");
 }