[PATCH] D141032: [Clang][RISCV] Expose vlenb to vread_csr

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

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This commit resolves: riscv-non-isa/rvv-intrinsic-doc#180


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D141032

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c


Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c
===================================================================
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c
@@ -40,3 +40,12 @@
 unsigned long vread_csr_vcsr(void) {
   return vread_csr(RVV_VCSR);
 }
+
+// CHECK-LABEL: @vread_csr_vlenb(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vlenb", "=r,~{memory}"() #[[ATTR1]], !srcloc !8
+// CHECK-NEXT:    ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vlenb(void) {
+  return vread_csr(RVV_VLENB);
+}
Index: clang/include/clang/Basic/riscv_vector.td
===================================================================
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -1516,6 +1516,7 @@
   RVV_VXSAT,
   RVV_VXRM,
   RVV_VCSR,
+  RVV_VLENB,
 };
 
 static __inline__ __attribute__((__always_inline__, __nodebug__))
@@ -1534,6 +1535,9 @@
     case RVV_VCSR:
       __asm__ __volatile__ ("csrr\t%0, vcsr" : "=r"(__rv) : : "memory");
       break;
+    case RVV_VLENB:
+      __asm__ __volatile__ ("csrr\t%0, vlenb" : "=r"(__rv) : : "memory");
+      break;
   }
   return __rv;
 }


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