[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

[Brandon Wu via Phabricator via cfe-commits]

4vtomat updated this revision to Diff 484226.
4vtomat added a comment.

Correct OPERAND_LAST_RISCV_IMM in OperandType


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138807/new/

https://reviews.llvm.org/D138807

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rvv/rv64zvkb.s
  llvm/test/MC/RISCV/rvv/rv64zvkg.s
  llvm/test/MC/RISCV/rvv/rv64zvknh.s
  llvm/test/MC/RISCV/rvv/rv64zvkns.s
  llvm/test/MC/RISCV/rvv/rv64zvkns_invalid.s
  llvm/test/MC/RISCV/rvv/rv64zvksed-invalid.s
  llvm/test/MC/RISCV/rvv/rv64zvksed.s
  llvm/test/MC/RISCV/rvv/rv64zvksh.s

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