[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

Ken has updated spec to clarify requirements of those vector crypto extensions: https://github.com/riscv/riscv-crypto/commit/40695306f628e6dc764d1d0f35392eac792d2c3b

  These Vector Crypto Extensions can be built on any RISC-V base. However, XLEN=32 implementations
  will only be able to provide 32 bit values to the .vx vector-scalar instructions. 
  
  With the exception of Zvknhb, each of these Vector Crypto Extensions can be build on _any_ 
  base Vector Extension, embedded (Zve*) or application ("V"). Zvknhb requires ELEN=64 and therefore cannot be implemented on a Zve32* base.
  
  While the Zvkb extension can be built on an Zve32* base, the vclmul[h] instructions will not be
  supported in such a case as they require SEW=64.
  ...


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138807/new/

https://reviews.llvm.org/D138807