[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

Craig Topper via Phabricator via cfe-commits cfe-commits at lists.llvm.org
Thu Nov 10 22:27:38 PST 2022


craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td:14
+//===----------------------------------------------------------------------===//
+// -XVentanaCondOps
+//===----------------------------------------------------------------------===//
----------------
Does the `-` here mean something?


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td:19
+  mayLoad = 0, mayStore = 0, isCodeGenOnly = 0, DecoderNamespace = "Ventana"
+  in {
+
----------------
I don't think we need to this applied to the class and the instantatiations of the class. I think you can drop the curly braces and only apply it to the class.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td:24
+              (ins GPR:$rs1, GPR:$rs2), opcodestr,
+              "$rd, $rs1, $rs2">{
+}
----------------
space between `>` and `{`


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137350/new/

https://reviews.llvm.org/D137350



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