[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps
Philip Reames via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Thu Nov 10 15:25:45 PST 2022
reames updated this revision to Diff 474620.
reames added a comment.
Address Kito's review comments
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D137350/new/
https://reviews.llvm.org/D137350
Files:
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/XVentanaCondOps-valid.s
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