[PATCH] D116735: [RISCV] Adjust RV64I data layout by using n32:64 in layout string

[Craig Topper via Phabricator via cfe-commits]

craig.topper updated this revision to Diff 471385.
craig.topper added a comment.

Refine ReleaseNotes


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116735/new/

https://reviews.llvm.org/D116735

Files:
  clang/lib/Basic/Targets/RISCV.h
  llvm/docs/ReleaseNotes.rst
  llvm/lib/IR/AutoUpgrade.cpp
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/aext-to-sext.ll
  llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll
  llvm/test/CodeGen/RISCV/loop-strength-reduce-loop-invar.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
  llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D116735.471385.patch
Type: text/x-patch
Size: 9685 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/cfe-commits/attachments/20221028/5ec30ebe/attachment-0001.bin>