[PATCH] D136040: [X86][1/2] Support PREFETCHI instructions

Tue Oct 18 20:41:31 PDT 2022

craig.topper added a comment.

Can the intrinsics changes be split from this patch so they don't depend on D136145 <https://reviews.llvm.org/D136145>. There's no reason to block assembler/disassembler support for that.

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Comment at: clang/lib/Headers/prfchiintrin.h:16
+/// Loads an instruction sequence containing the specified memory address into
+///    all level cache.
+///
----------------
It looks old that this indented differently than the "Loads" on the line above.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136040/new/

https://reviews.llvm.org/D136040