[PATCH] D136040: [X86] Support PREFETCHI instructions

[Phoebe Wang via Phabricator via cfe-commits]

pengfei added a comment.

In D136040#3862265 <https://reviews.llvm.org/D136040#3862265>, @uweigand wrote:

> In D136040#3862225 <https://reviews.llvm.org/D136040#3862225>, @pengfei wrote:
>
>> 3. Add semacheck for prefetch write to instruction cache;
>>
>> I think the affected ARM and SystemZ tests are not valid before. Could @t.p.northover and @uweigand help to have a look?
>
> This seems to be a semantic change.   The Language Reference does not spell out that a write prefetch on the instruction cache is prohibited.  In fact, I read it to explicitly state that every flavor of the prefetch intrinsic that doesn't match anything supported on the target architecture should simply be a no-op.  (I could imagine that on certain architectures, you might even have such a prefetch, e.g. to handle self-modifying code more efficiently.)

Sure, it is possible. But at least for now, there's no real target requires it. Checked with `grep -rwn 'llvm.prefetch.*i32 0\s*)' llvm/test/CodeGen/`.
The reason I do it is it's ambiguity to backend when lower it to a target that has "write data", "read data" and "read instruction" prefetches. It's clear if we just support the semantic of "read instruction" and lower it to "read data" when available.
I think we can modify Language Reference for it.


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  https://reviews.llvm.org/D136040/new/

https://reviews.llvm.org/D136040