[PATCH] D121779: [RISCV] Add zihintntl compressed instructions

[Cao Shun via Phabricator via cfe-commits]

alextsao1999 marked an inline comment as done.
alextsao1999 added inline comments.


================
Comment at: llvm/test/MC/RISCV/rv32zihintntlc-valid.s:42
+# CHECK-ASM: encoding: [0x16,0x90]
+c.ntl.all
----------------
kito-cheng wrote:
> Could you add an invalid check for `c.ntl` instruction to make sure they can't use without `C`? 
> e.g. `-mattr=+experimental-zihintntl` but no `+c`.
Done


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121779/new/

https://reviews.llvm.org/D121779