[PATCH] D128712: [clang-format] Handle Verilog modules

[sstwcw via Phabricator via cfe-commits]

sstwcw marked 2 inline comments as done.
sstwcw added inline comments.


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Comment at: clang/lib/Format/UnwrappedLineParser.cpp:4072
+                                Keywords.kw_randsequence)) {
+    AddLevels += Style.IndentCaseLabels;
+    nextToken();
----------------
HazardyKnusperkeks wrote:
> Using `bool`s in integer expressions has caused some trouble in code I've seen. I'd prefer to use it as boolean.
I am sorry.  I should have fixed it myself since you had already pointed it out several times.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128712/new/

https://reviews.llvm.org/D128712