[PATCH] D124749: [clang-format] Handle Verilog preprocessor directives

[sstwcw via Phabricator via cfe-commits]

sstwcw updated this revision to Diff 433614.
sstwcw added a comment.

- use raw string for regex
- use default style in test
- remove parentheses
- use seek now that skipOver no longer exists


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124749/new/

https://reviews.llvm.org/D124749

Files:
  clang/lib/Format/FormatToken.h
  clang/lib/Format/FormatTokenLexer.cpp
  clang/lib/Format/FormatTokenLexer.h
  clang/lib/Format/TokenAnnotator.cpp
  clang/lib/Format/UnwrappedLineParser.cpp
  clang/unittests/Format/FormatTestVerilog.cpp

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