[PATCH] D124749: [clang-format] Handle Verilog preprocessor directives

Wed Jun 1 18:35:04 PDT 2022

sstwcw marked 5 inline comments as done.
sstwcw added inline comments.

================
Comment at: clang/unittests/Format/FormatTestVerilog.cpp:179
+  verifyFormat("`x = (`x1 + `x2 + x);");
+  // Lines starting with a preprocessor directive should not be indented.
+  std::string Directives[] = {
----------------
>>>! In D124749#3490834, @MyDeveloperDay wrote:
>> You add significant number of keywords here but I don't see any of them being tested? can you add a unit tests to cover what you are adding
> 
> I think this is still open?
The keywords added in this revision are tested here. Most of those added in D123450 don't have tests, but I haven't added stuff to handle them yet.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124749/new/

https://reviews.llvm.org/D124749