[PATCH] D125875: [RISCV] Add vread_csr and vwrite_csr to riscv_vector.h
Craig Topper via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Wed May 18 16:55:18 PDT 2022
craig.topper added inline comments.
================
Comment at: clang/include/clang/Basic/riscv_vector.td:1511
+__extension__ extern __inline
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+unsigned long vread_csr(enum RVV_CSR csr) {
----------------
Do we need __gnu_inline__ and __artificial__? The only intrinsics headers that have them in clang are in ppc_wrappers. X86 uses `__attribute__((__always_inline__, __nodebug__`
================
Comment at: clang/include/clang/Basic/riscv_vector.td:1512
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+unsigned long vread_csr(enum RVV_CSR csr) {
+ unsigned long rv = 0;
----------------
X86 and arm_neon.h uses double underscore prefixes on all variables in intrinsic headers to reduce the chance of a collision with a user having a macro with the same name.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D125875/new/
https://reviews.llvm.org/D125875
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