[PATCH] D123450: [clang-format] Parse Verilog if statements

[Björn Schäpers via Phabricator via cfe-commits]

HazardyKnusperkeks added inline comments.


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Comment at: clang/lib/Format/FormatToken.h:374
+  /// Verilog we want to treat the backtick like a hash.
+  tok::TokenKind AliasToken = tok::unknown;
+
----------------
Can't we do that with a type?

I'm not very happy about the alias, because you can still call `Tok.getKind()`.


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Comment at: clang/lib/Format/FormatToken.h:1157
+    VerilogExtraKeywords = std::unordered_set<IdentifierInfo *>(
+        {kw_always,       kw_always_comb,  kw_always_ff,    kw_always_latch,
+         kw_assert,       kw_assign,       kw_assume,       kw_automatic,
----------------
sstwcw wrote:
> Does anyone know why this part gets aligned unlike the two lists above?
Have you reformatted the other lines with the same config and revision?
If yes, my guess would be the missing comment.


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Comment at: clang/lib/Format/FormatToken.h:1533
+    switch (Tok.Tok.getKind()) {
+    case tok::kw_case:
+    case tok::kw_class:
----------------
So you have a blacklist what is not a keyword? Seems a bit non future proof, new C++ keywords would have to be added here.


================
Comment at: clang/lib/Format/FormatToken.h:1593
+
+  std::unordered_set<IdentifierInfo *> VerilogExtraKeywords;
 };
----------------
For consistency reasons add the comment like above.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D123450/new/

https://reviews.llvm.org/D123450