[PATCH] D123450: [clang-format] Parse Verilog if statements

[sstwcw via Phabricator via cfe-commits]

sstwcw added inline comments.


================
Comment at: clang/lib/Format/FormatToken.h:1157
+    VerilogExtraKeywords = std::unordered_set<IdentifierInfo *>(
+        {kw_always,       kw_always_comb,  kw_always_ff,    kw_always_latch,
+         kw_assert,       kw_assign,       kw_assume,       kw_automatic,
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Does anyone know why this part gets aligned unlike the two lists above?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123450/new/

https://reviews.llvm.org/D123450