[clang] 5dc0a16 - [PowerPC] Fix __builtin_pdepd and __builtin_pextd to be 64-bit and P10 only.

[Amy Kwan via cfe-commits]

Author: Amy Kwan
Date: 2022-02-15T12:30:50-06:00
New Revision: 5dc0a1657be14df68bfc33deb2fb75476acdaec8

URL: https://github.com/llvm/llvm-project/commit/5dc0a1657be14df68bfc33deb2fb75476acdaec8
DIFF: https://github.com/llvm/llvm-project/commit/5dc0a1657be14df68bfc33deb2fb75476acdaec8.diff

LOG: [PowerPC] Fix __builtin_pdepd and __builtin_pextd to be 64-bit and P10 only.

The `__builtin_pdepd` and `__builtin_pextd` are P10 builtins that are meant to
be used under 64-bit only. For instance, when the builtins are compiled under
32-bit mode:
```
$ cat t.c
unsigned long long foo(unsigned long long a, unsigned long long b) {
  return __builtin_pextd(a,b);
}

$ clang -c t.c -mcpu=pwr10 -m32
ExpandIntegerResult #0: t31: i64 = llvm.ppc.pextd TargetConstant:i32<6928>, t28, t29

fatal error: error in backend: Do not know how to expand the result of this operator!
```
This patch adds sema checking for these builtins to compile under 64-bit
mode only and on P10. The builtins will emit a diagnostic when they are compiled on
non-P10 compilations and on 32-bit mode.

Differential Revision: https://reviews.llvm.org/D118753

Added: 
    clang/test/CodeGen/PowerPC/builtins-ppc-pwr10-64bit.c

Modified: 
    clang/lib/Sema/SemaChecking.cpp
    llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll

Removed: 
    


################################################################################
diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index c422981a1a2e6..cb65991cbe2e9 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3604,6 +3604,8 @@ static bool isPPC_64Builtin(unsigned BuiltinID) {
   case PPC::BI__builtin_divde:
   case PPC::BI__builtin_divdeu:
   case PPC::BI__builtin_bpermd:
+  case PPC::BI__builtin_pdepd:
+  case PPC::BI__builtin_pextd:
   case PPC::BI__builtin_ppc_ldarx:
   case PPC::BI__builtin_ppc_stdcx:
   case PPC::BI__builtin_ppc_tdw:
@@ -3763,6 +3765,10 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
   case PPC::BI__builtin_pack_vector_int128:
     return SemaFeatureCheck(*this, TheCall, "vsx",
                             diag::err_ppc_builtin_only_on_arch, "7");
+  case PPC::BI__builtin_pdepd:
+  case PPC::BI__builtin_pextd:
+    return SemaFeatureCheck(*this, TheCall, "isa-v31-instructions",
+                            diag::err_ppc_builtin_only_on_arch, "10");
   case PPC::BI__builtin_altivec_vgnb:
      return SemaBuiltinConstantArgRange(TheCall, 1, 2, 7);
   case PPC::BI__builtin_altivec_vec_replace_elt:

diff  --git a/clang/test/CodeGen/PowerPC/builtins-ppc-pwr10-64bit.c b/clang/test/CodeGen/PowerPC/builtins-ppc-pwr10-64bit.c
new file mode 100644
index 0000000000000..c6922eae6bf58
--- /dev/null
+++ b/clang/test/CodeGen/PowerPC/builtins-ppc-pwr10-64bit.c
@@ -0,0 +1,34 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -emit-llvm %s \
+// RUN:   -target-cpu pwr10 -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -emit-llvm %s \
+// RUN:   -target-cpu pwr10 -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -emit-llvm %s \
+// RUN:   -target-cpu pwr10 -o - | FileCheck %s
+// RUN: not %clang_cc1 -triple powerpc-unknown-aix -emit-llvm-only %s \
+// RUN:   -target-cpu pwr8 2>&1 | FileCheck %s --check-prefix=CHECK-32-ERROR
+// RUN: not %clang_cc1 -triple powerpc-unknown-linux-gnu -emit-llvm-only %s \
+// RUN:   -target-cpu pwr9 2>&1 | FileCheck %s --check-prefix=CHECK-32-ERROR
+// RUN: not %clang_cc1 -triple powerpc64-unknown-aix -emit-llvm-only %s \
+// RUN:   -target-cpu pwr9 2>&1 | FileCheck %s --check-prefix=CHECK-NONPWR10-ERR
+// RUN: not %clang_cc1 -triple powerpc64-unknown-linux-gnu -emit-llvm-only %s \
+// RUN:   -target-cpu pwr8 2>&1 | FileCheck %s --check-prefix=CHECK-NONPWR10-ERR
+
+extern unsigned long long ull;
+
+unsigned long long test_builtin_pextd() {
+  // CHECK-LABEL:    @test_builtin_pextd(
+  // CHECK:          %2 = call i64 @llvm.ppc.pextd(i64 %0, i64 %1)
+  // CHECK-32-ERROR: error: this builtin is only available on 64-bit targets
+  // CHECK-NONPWR10-ERR:  error: this builtin is only valid on POWER10 or later CPUs
+  return __builtin_pextd(ull, ull);
+}
+
+unsigned long long test_builtin_pdepd() {
+  // CHECK-LABEL:    @test_builtin_pdepd(
+  // CHECK:          %2 = call i64 @llvm.ppc.pdepd(i64 %0, i64 %1)
+  // CHECK-32-ERROR: error: this builtin is only available on 64-bit targets
+  // CHECK-NONPWR10-ERR:  error: this builtin is only valid on POWER10 or later CPUs
+  return __builtin_pdepd(ull, ull);
+}
+

diff  --git a/llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll b/llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll
index 901b449bb5c39..4643faee88db1 100644
--- a/llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll
+++ b/llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll
@@ -2,6 +2,9 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN:   FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s
 
 ; These test cases aim to test the bit manipulation operations on Power10.