[PATCH] D112408: [WIP][RISCV] Add the zve extension according to the v1.0-rc2 spec

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll:158
 ; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    lui a1, 1048560
+; CHECK-NEXT:    or a0, a0, a1
----------------
frasercrmck wrote:
> What's going on here, do you know?
I believe this is coming from the nan-boxing for f16 in RISCVTargetLowering::splitValueIntoRegisterParts. The addition of +f must have changed PartVT from i32/i64 to f32. Even though we're using i32 for the return due to ABI.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112408/new/

https://reviews.llvm.org/D112408