[PATCH] D103668: [PowerPC] Implement trap and conversion builtins for XL compatibility

[Albion Fung via Phabricator via cfe-commits]

Conanap marked an inline comment as done.
Conanap added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1733
+// as XL produces a tweq <regA>, <regA>.
+def : Pat<(int_ppc_tdw g8rc:$A, g8rc:$B, 31),
+          (TD 4, $A, $B)>;
----------------
nemanjai wrote:
> This is supposed to be an unconditional trap and the produced sequence is not that.
this one is quite weird... I see the output on `xlC` as `tdnei`:
`0b 04 00 00     tdnei   r4,0`

Also for the `tdne` pattern that I removed (`TD 3, ...`), `xlC` outputs the same encoding for `TD 3` and `TD 24`:  

```
Disassembly of section .text:

0000000000000000 <.yes>:
   0:   7f 03 20 88     tdne    r3,r4
   4:   4e 80 00 20     blr
   8:   00 00 00 00     .long 0x0
   c:   00 00 20 00     .long 0x2000
  10:   00 00 00 00     .long 0x0
  14:   00 00 00 08     .long 0x8
        ...
void yes(long long a, long long b) {
   return __tdw(a, b, 24);
}
```

and for 3:
```
Disassembly of section .text:

0000000000000000 <.yes>:
   0:   7f 03 20 88     tdne    r3,r4
   4:   4e 80 00 20     blr
   8:   00 00 00 00     .long 0x0
   c:   00 00 20 00     .long 0x2000
  10:   00 00 00 00     .long 0x0
  14:   00 00 00 08     .long 0x8
        ...
void yes(long long a, long long b) {
   return __tdw(a, b, 3);
}
```


Repository:
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  https://reviews.llvm.org/D103668/new/

https://reviews.llvm.org/D103668