[PATCH] D105142: RFC: Implementing new mechanism for hard register operands to inline asm as a constraint.

[Fangrui Song via Phabricator via cfe-commits]

MaskRay added subscribers: rampitec, arsenm.
MaskRay added a comment.

This is great.

  unsigned long foo(unsigned long addr, unsigned long a0,
                    unsigned long a1, unsigned long a2,
                    unsigned long a3, unsigned long a4,
                    unsigned long a5) {
    unsigned long result asm("rax");
    unsigned long b2 asm("rdx") = a2;
    unsigned long b3 asm("rcx") = a3;
    unsigned long b4 asm("r8") = a4;
    unsigned long b5 asm("r9") = a5;
    asm("call *%1" : "=r" (result) : "{rax}"(addr), "{rdi}"(a0), "{rsi}"(a1), "r"(b2), "r"(b3), "r"(b4), "r"(b5));
    return result;
  }

this compiles to`%0 = tail call i64 asm "call *$1", "=r,{r{ax}x},{r{dx}i},{rsi},r,r,r,r,~{dirflag},~{fpsr},~{flags}"(i64 %addr, i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, i64 %a5) #1, !srcloc !3`
(note `{r{ax}x},{r{dx}i}`) which will cause a backend failure `error: couldn't allocate input reg for constraint '{r{dx}'`.
Can you investigate it?

> For example the AMDGPU target. It supports syntax of the form {register-name} as well as {register-name[...]}.

CC @arsenm @rampitec for AMDGPU thoughts.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D105142/new/

https://reviews.llvm.org/D105142