[PATCH] D105254: [RISCV] Support machine constraint "S"
Jessica Clarke via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Wed Jun 30 19:32:11 PDT 2021
jrtc27 added inline comments.
================
Comment at: llvm/test/CodeGen/RISCV/inline-asm-S-constraint.ll:24
+; RV64-NEXT: ret
+entry:
+ %0 = tail call i8* asm "lui $0, %hi($1)\0Aaddi $0,$0,%lo($1)", "=r,S"(i32* nonnull @var)
----------------
MaskRay wrote:
> jrtc27 wrote:
> > Label isn't needed
> Omitting the entry label is allowed but having a label is canonical. Without it `%0` needs to be `%1`.
TIL
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D105254/new/
https://reviews.llvm.org/D105254
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