[PATCH] D100448: [RISCV][Clang] Add RVV AMO builtins

[ShihPo Hung via Phabricator via cfe-commits]

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Add vamo[swap/add/xor/and/or/min/max/minu/maxu] builtins.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D100448

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vamoadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vamoand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vamomax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vamomin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vamoor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vamoswap.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vamoxor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vamoadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vamoand.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vamomax.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vamomin.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vamoor.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vamoswap.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vamoxor.c
  clang/utils/TableGen/RISCVVEmitter.cpp