[PATCH] D99669: [RISCV][Clang] Add more RVV Floating-Point intrinsic functions.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.


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Comment at: clang/include/clang/Basic/riscv_vector.td:315
+multiclass RVVFloatingWidenTerBuiltinSet {
+  let HasMaskedOffOperand = false, Log2LMUL = [-2, -1, 0, 1, 2] in {
+    defm "" : RVVOutOp1Op2BuiltinSet<NAME, "f",
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khchen wrote:
> HsiangKai wrote:
> > why is there not -3 in Log2LMUL?
> Because there is no vector floating type with `mf8`. 
> The minimum faction LMUL for floating is `mf2` and half float is `mf4`.
> In fact, we can give all LMUL combinations because the clang generator will make sure the type is legal.
Since we're not generating "h" here it should either be all LMULs or remove -2 as well.


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Comment at: clang/include/clang/Basic/riscv_vector.td:816
 // 14.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
-// TODO
+defm vfmacc : RVVFloatingTerBuiltinSet;
+defm vfnmacc : RVVFloatingTerBuiltinSet;
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Can we line up the colons here so that RVVFloatingTerBuiltinSet is in the same place in every line?


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Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c:54
+                                  size_t vl) {
+  return vfwadd(op1, op2, vl);
+}
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Are we going to fix the inconsistency with vfwadd_vf?


Repository:
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  https://reviews.llvm.org/D99669/new/

https://reviews.llvm.org/D99669