[PATCH] D99669: [RISCV][Clang] Add more RVV Floating-Point intrinsic functions.
Zakk Chen via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Tue Apr 6 06:43:34 PDT 2021
khchen marked 2 inline comments as done.
khchen added inline comments.
================
Comment at: clang/include/clang/Basic/riscv_vector.td:315
+multiclass RVVFloatingWidenTerBuiltinSet {
+ let HasMaskedOffOperand = false, Log2LMUL = [-2, -1, 0, 1, 2] in {
+ defm "" : RVVOutOp1Op2BuiltinSet<NAME, "f",
----------------
HsiangKai wrote:
> why is there not -3 in Log2LMUL?
Because there is no vector floating type with `mf8`.
The minimum faction LMUL for floating is `mf2` and half float is `mf4`.
In fact, we can give all LMUL combinations because the clang generator will make sure the type is legal.
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D99669/new/
https://reviews.llvm.org/D99669
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