[PATCH] D98616: [RISCV] Add inline asm constraint 'v' in Clang for RISC-V 'V'.

[Jessica Clarke via Phabricator via cfe-commits]

jrtc27 added a comment.

In D98616#2626094 <https://reviews.llvm.org/D98616#2626094>, @jrtc27 wrote:

> In D98616#2626093 <https://reviews.llvm.org/D98616#2626093>, @kito-cheng wrote:
>
>> GCC use `vr` for vector register and `vm` for vector mask register.
>
> How does that even work? Aren't multi character strings a set of options?

Hm, apparently multi-character constraints already exist. Not a fan of it as it parses like "vector or register/memory" to me but if that's how GCC needs to internally model its instructions then we have to copy that...


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