[PATCH] D89972: Add pipeline model for HiSilicon's TSV110
Elvina Yakubova via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Thu Oct 22 10:09:47 PDT 2020
Elvina created this revision.
Elvina added reviewers: bryanpkc, kristof.beyls, t.p.northover, SjoerdMeijer.
Elvina added projects: LLVM, clang.
Herald added subscribers: cfe-commits, jfb, hiraditya.
Elvina requested review of this revision.
This patch adds the scheduling and cost model for TSV110.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D89972
Files:
clang/test/Driver/aarch64-cpus.c
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64SchedTSV110.td
llvm/lib/Target/AArch64/AArch64SchedTSV110Details.td
llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
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