[PATCH] D88759: [RISCV] Add SiFive cores to the CPU option

Nico Weber via Phabricator via cfe-commits cfe-commits at lists.llvm.org
Mon Oct 5 17:35:35 PDT 2020

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thakis added a comment.

This seems to break tests: http://45.33.8.238/linux/29545/step_7.txt

Can you take a look and revert for now if it takes a while to fix?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88759/new/

https://reviews.llvm.org/D88759

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