[PATCH] D59615: [AArch64] When creating SISD intrinsic calls widen scalar args into a zero vectors, not undef

Amara Emerson via Phabricator via cfe-commits cfe-commits at lists.llvm.org
Fri Aug 14 03:31:13 PDT 2020

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aemerson abandoned this revision.
aemerson added a comment.

Seems no one is enthusiastic about this change, so I'm going to drop it.


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  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D59615/new/

https://reviews.llvm.org/D59615

Previous message: [PATCH] D59615: [AArch64] When creating SISD intrinsic calls widen scalar args into a zero vectors, not undef
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