[PATCH] D59615: [AArch64] When creating SISD intrinsic calls widen scalar args into a zero vectors, not undef

[Amara Emerson via Phabricator via cfe-commits]

aemerson added a comment.
Herald added a subscriber: danielkiss.

Does anyone object to this? I'd like to get it off my review dashboard one way or the other.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D59615/new/

https://reviews.llvm.org/D59615