[clang] b32d14c - [SveEmitter] Add builtins for SVE2 uniform DSP operations
Sander de Smalen via cfe-commits
cfe-commits at lists.llvm.org
Thu May 7 05:34:53 PDT 2020
Author: Sander de Smalen
Date: 2020-05-07T13:31:46+01:00
New Revision: b32d14c30e45dd60df435456b4e6747fd83590bb
URL: https://github.com/llvm/llvm-project/commit/b32d14c30e45dd60df435456b4e6747fd83590bb
DIFF: https://github.com/llvm/llvm-project/commit/b32d14c30e45dd60df435456b4e6747fd83590bb.diff
LOG: [SveEmitter] Add builtins for SVE2 uniform DSP operations
This patch adds builtins for:
- svqadd, svhadd, svrhadd
- svqsub, svhsub, svqusbr, svhsubr
- svqabs
- svqneg
- svrecpe
- svrsqrte
Added:
clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_hadd.c
clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_hsub.c
clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_hsubr.c
clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qabs.c
clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qadd.c
clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qneg.c
clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qsub.c
clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qsubr.c
clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_recpe.c
clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rhadd.c
clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rsqrte.c
Modified:
clang/include/clang/Basic/arm_sve.td
Removed:
################################################################################
diff --git a/clang/include/clang/Basic/arm_sve.td b/clang/include/clang/Basic/arm_sve.td
index 4b43e02b3367..07af044ce1de 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -1248,6 +1248,32 @@ def SVWHILEHS_U32 : SInst<"svwhilege_{d}[_{1}]", "Pmm", "PUcPUsPUiPUl", MergeNon
def SVWHILEHS_U64 : SInst<"svwhilege_{d}[_{1}]", "Pnn", "PUcPUsPUiPUl", MergeNone, "aarch64_sve_whilehs", [IsOverloadWhile]>;
}
+////////////////////////////////////////////////////////////////////////////////
+// SVE2 - Uniform DSP operations
+
+let ArchGuard = "defined(__ARM_FEATURE_SVE2)" in {
+defm SVQADD_S : SInstZPZZ<"svqadd", "csli", "aarch64_sve_sqadd">;
+defm SVQADD_U : SInstZPZZ<"svqadd", "UcUsUiUl", "aarch64_sve_uqadd">;
+defm SVHADD_S : SInstZPZZ<"svhadd", "csli", "aarch64_sve_shadd">;
+defm SVHADD_U : SInstZPZZ<"svhadd", "UcUsUiUl", "aarch64_sve_uhadd">;
+defm SVRHADD_S : SInstZPZZ<"svrhadd", "csli", "aarch64_sve_srhadd">;
+defm SVRHADD_U : SInstZPZZ<"svrhadd", "UcUsUiUl", "aarch64_sve_urhadd">;
+
+defm SVQSUB_S : SInstZPZZ<"svqsub", "csli", "aarch64_sve_sqsub">;
+defm SVQSUB_U : SInstZPZZ<"svqsub", "UcUsUiUl", "aarch64_sve_uqsub">;
+defm SVQSUBR_S : SInstZPZZ<"svqsubr", "csli", "aarch64_sve_sqsubr">;
+defm SVQSUBR_U : SInstZPZZ<"svqsubr", "UcUsUiUl", "aarch64_sve_uqsubr">;
+defm SVHSUB_S : SInstZPZZ<"svhsub", "csli", "aarch64_sve_shsub">;
+defm SVHSUB_U : SInstZPZZ<"svhsub", "UcUsUiUl", "aarch64_sve_uhsub">;
+defm SVHSUBR_S : SInstZPZZ<"svhsubr", "csli", "aarch64_sve_shsubr">;
+defm SVHSUBR_U : SInstZPZZ<"svhsubr", "UcUsUiUl", "aarch64_sve_uhsubr">;
+
+defm SVQABS : SInstZPZ<"svqabs", "csil", "aarch64_sve_sqabs">;
+defm SVQNEG : SInstZPZ<"svqneg", "csil", "aarch64_sve_sqneg">;
+defm SVRECPE : SInstZPZ<"svrecpe", "Ui", "aarch64_sve_urecpe">;
+defm SVRSQRTE : SInstZPZ<"svrsqrte", "Ui", "aarch64_sve_ursqrte">;
+}
+
////////////////////////////////////////////////////////////////////////////////
// SVE2 - Non-temporal gather/scatter
let ArchGuard = "defined(__ARM_FEATURE_SVE2)" in {
diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_hadd.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_hadd.c
new file mode 100644
index 000000000000..6a9f3f347f63
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_hadd.c
@@ -0,0 +1,569 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s
+
+#include <arm_sve.h>
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+svint8_t test_svhadd_s8_m(svbool_t pg, svint8_t op1, svint8_t op2)
+{
+ // CHECK-LABEL: test_svhadd_s8_m
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.shadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_s8_m'}}
+ return SVE_ACLE_FUNC(svhadd,_s8,_m,)(pg, op1, op2);
+}
+
+svint16_t test_svhadd_s16_m(svbool_t pg, svint16_t op1, svint16_t op2)
+{
+ // CHECK-LABEL: test_svhadd_s16_m
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.shadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_s16_m'}}
+ return SVE_ACLE_FUNC(svhadd,_s16,_m,)(pg, op1, op2);
+}
+
+svint32_t test_svhadd_s32_m(svbool_t pg, svint32_t op1, svint32_t op2)
+{
+ // CHECK-LABEL: test_svhadd_s32_m
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.shadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_s32_m'}}
+ return SVE_ACLE_FUNC(svhadd,_s32,_m,)(pg, op1, op2);
+}
+
+svint64_t test_svhadd_s64_m(svbool_t pg, svint64_t op1, svint64_t op2)
+{
+ // CHECK-LABEL: test_svhadd_s64_m
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.shadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_s64_m'}}
+ return SVE_ACLE_FUNC(svhadd,_s64,_m,)(pg, op1, op2);
+}
+
+svuint8_t test_svhadd_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2)
+{
+ // CHECK-LABEL: test_svhadd_u8_m
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uhadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_u8_m'}}
+ return SVE_ACLE_FUNC(svhadd,_u8,_m,)(pg, op1, op2);
+}
+
+svuint16_t test_svhadd_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2)
+{
+ // CHECK-LABEL: test_svhadd_u16_m
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uhadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_u16_m'}}
+ return SVE_ACLE_FUNC(svhadd,_u16,_m,)(pg, op1, op2);
+}
+
+svuint32_t test_svhadd_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2)
+{
+ // CHECKA-LABEL: test_svhadd_u32_m
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uhadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_u32_m'}}
+ return SVE_ACLE_FUNC(svhadd,_u32,_m,)(pg, op1, op2);
+}
+
+svuint64_t test_svhadd_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2)
+{
+ // CHECK-LABEL: test_svhadd_u64_m
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uhadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_u64_m'}}
+ return SVE_ACLE_FUNC(svhadd,_u64,_m,)(pg, op1, op2);
+}
+
+svint8_t test_svhadd_n_s8_m(svbool_t pg, svint8_t op1, int8_t op2)
+{
+ // CHECK-LABEL: test_svhadd_n_s8_m
+ // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.shadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_n_s8_m'}}
+ return SVE_ACLE_FUNC(svhadd,_n_s8,_m,)(pg, op1, op2);
+}
+
+svint16_t test_svhadd_n_s16_m(svbool_t pg, svint16_t op1, int16_t op2)
+{
+ // CHECK-LABEL: test_svhadd_n_s16_m
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.shadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_n_s16_m'}}
+ return SVE_ACLE_FUNC(svhadd,_n_s16,_m,)(pg, op1, op2);
+}
+
+svint32_t test_svhadd_n_s32_m(svbool_t pg, svint32_t op1, int32_t op2)
+{
+ // CHECK-LABEL: test_svhadd_n_s32_m
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.shadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_n_s32_m'}}
+ return SVE_ACLE_FUNC(svhadd,_n_s32,_m,)(pg, op1, op2);
+}
+
+svint64_t test_svhadd_n_s64_m(svbool_t pg, svint64_t op1, int64_t op2)
+{
+ // CHECK-LABEL: test_svhadd_n_s64_m
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.shadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_n_s64_m'}}
+ return SVE_ACLE_FUNC(svhadd,_n_s64,_m,)(pg, op1, op2);
+}
+
+svuint8_t test_svhadd_n_u8_m(svbool_t pg, svuint8_t op1, uint8_t op2)
+{
+ // CHECK-LABEL: test_svhadd_n_u8_m
+ // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uhadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_n_u8_m'}}
+ return SVE_ACLE_FUNC(svhadd,_n_u8,_m,)(pg, op1, op2);
+}
+
+svuint16_t test_svhadd_n_u16_m(svbool_t pg, svuint16_t op1, uint16_t op2)
+{
+ // CHECK-LABEL: test_svhadd_n_u16_m
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uhadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_n_u16_m'}}
+ return SVE_ACLE_FUNC(svhadd,_n_u16,_m,)(pg, op1, op2);
+}
+
+svuint32_t test_svhadd_n_u32_m(svbool_t pg, svuint32_t op1, uint32_t op2)
+{
+ // CHECK-LABEL: test_svhadd_n_u32_m
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uhadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_n_u32_m'}}
+ return SVE_ACLE_FUNC(svhadd,_n_u32,_m,)(pg, op1, op2);
+}
+
+svuint64_t test_svhadd_n_u64_m(svbool_t pg, svuint64_t op1, uint64_t op2)
+{
+ // CHECK-LABEL: test_svhadd_n_u64_m
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uhadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_n_u64_m'}}
+ return SVE_ACLE_FUNC(svhadd,_n_u64,_m,)(pg, op1, op2);
+}
+
+svint8_t test_svhadd_s8_z(svbool_t pg, svint8_t op1, svint8_t op2)
+{
+ // CHECK-LABEL: test_svhadd_s8_z
+ // CHECK: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.shadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_s8_z'}}
+ return SVE_ACLE_FUNC(svhadd,_s8,_z,)(pg, op1, op2);
+}
+
+svint16_t test_svhadd_s16_z(svbool_t pg, svint16_t op1, svint16_t op2)
+{
+ // CHECK-LABEL: test_svhadd_s16_z
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.shadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_s16_z'}}
+ return SVE_ACLE_FUNC(svhadd,_s16,_z,)(pg, op1, op2);
+}
+
+svint32_t test_svhadd_s32_z(svbool_t pg, svint32_t op1, svint32_t op2)
+{
+ // CHECK-LABEL: test_svhadd_s32_z
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.shadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_s32_z'}}
+ return SVE_ACLE_FUNC(svhadd,_s32,_z,)(pg, op1, op2);
+}
+
+svint64_t test_svhadd_s64_z(svbool_t pg, svint64_t op1, svint64_t op2)
+{
+ // CHECK-LABEL: test_svhadd_s64_z
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.shadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_s64_z'}}
+ return SVE_ACLE_FUNC(svhadd,_s64,_z,)(pg, op1, op2);
+}
+
+svuint8_t test_svhadd_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2)
+{
+ // CHECK-LABEL: test_svhadd_u8_z
+ // CHECK: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uhadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_u8_z'}}
+ return SVE_ACLE_FUNC(svhadd,_u8,_z,)(pg, op1, op2);
+}
+
+svuint16_t test_svhadd_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2)
+{
+ // CHECK-LABEL: test_svhadd_u16_z
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uhadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_u16_z'}}
+ return SVE_ACLE_FUNC(svhadd,_u16,_z,)(pg, op1, op2);
+}
+
+svuint32_t test_svhadd_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2)
+{
+ // CHECKA-LABEL: test_svhadd_u32_z
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uhadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_u32_z'}}
+ return SVE_ACLE_FUNC(svhadd,_u32,_z,)(pg, op1, op2);
+}
+
+svuint64_t test_svhadd_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2)
+{
+ // CHECK-LABEL: test_svhadd_u64_z
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uhadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_u64_z'}}
+ return SVE_ACLE_FUNC(svhadd,_u64,_z,)(pg, op1, op2);
+}
+
+svint8_t test_svhadd_n_s8_z(svbool_t pg, svint8_t op1, int8_t op2)
+{
+ // CHECK-LABEL: test_svhadd_n_s8_z
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.shadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_n_s8_z'}}
+ return SVE_ACLE_FUNC(svhadd,_n_s8,_z,)(pg, op1, op2);
+}
+
+svint16_t test_svhadd_n_s16_z(svbool_t pg, svint16_t op1, int16_t op2)
+{
+ // CHECK-LABEL: test_svhadd_n_s16_z
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.shadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_n_s16_z'}}
+ return SVE_ACLE_FUNC(svhadd,_n_s16,_z,)(pg, op1, op2);
+}
+
+svint32_t test_svhadd_n_s32_z(svbool_t pg, svint32_t op1, int32_t op2)
+{
+ // CHECK-LABEL: test_svhadd_n_s32_z
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.shadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_n_s32_z'}}
+ return SVE_ACLE_FUNC(svhadd,_n_s32,_z,)(pg, op1, op2);
+}
+
+svint64_t test_svhadd_n_s64_z(svbool_t pg, svint64_t op1, int64_t op2)
+{
+ // CHECK-LABEL: test_svhadd_n_s64_z
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.shadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_n_s64_z'}}
+ return SVE_ACLE_FUNC(svhadd,_n_s64,_z,)(pg, op1, op2);
+}
+
+svuint8_t test_svhadd_n_u8_z(svbool_t pg, svuint8_t op1, uint8_t op2)
+{
+ // CHECK-LABEL: test_svhadd_n_u8_z
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uhadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_n_u8_z'}}
+ return SVE_ACLE_FUNC(svhadd,_n_u8,_z,)(pg, op1, op2);
+}
+
+svuint16_t test_svhadd_n_u16_z(svbool_t pg, svuint16_t op1, uint16_t op2)
+{
+ // CHECK-LABEL: test_svhadd_n_u16_z
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uhadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_n_u16_z'}}
+ return SVE_ACLE_FUNC(svhadd,_n_u16,_z,)(pg, op1, op2);
+}
+
+svuint32_t test_svhadd_n_u32_z(svbool_t pg, svuint32_t op1, uint32_t op2)
+{
+ // CHECK-LABEL: test_svhadd_n_u32_z
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uhadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_n_u32_z'}}
+ return SVE_ACLE_FUNC(svhadd,_n_u32,_z,)(pg, op1, op2);
+}
+
+svuint64_t test_svhadd_n_u64_z(svbool_t pg, svuint64_t op1, uint64_t op2)
+{
+ // CHECK-LABEL: test_svhadd_n_u64_z
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uhadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_n_u64_z'}}
+ return SVE_ACLE_FUNC(svhadd,_n_u64,_z,)(pg, op1, op2);
+}
+
+svint8_t test_svhadd_s8_x(svbool_t pg, svint8_t op1, svint8_t op2)
+{
+ // CHECK-LABEL: test_svhadd_s8_x
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.shadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_s8_x'}}
+ return SVE_ACLE_FUNC(svhadd,_s8,_x,)(pg, op1, op2);
+}
+
+svint16_t test_svhadd_s16_x(svbool_t pg, svint16_t op1, svint16_t op2)
+{
+ // CHECK-LABEL: test_svhadd_s16_x
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.shadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_s16_x'}}
+ return SVE_ACLE_FUNC(svhadd,_s16,_x,)(pg, op1, op2);
+}
+
+svint32_t test_svhadd_s32_x(svbool_t pg, svint32_t op1, svint32_t op2)
+{
+ // CHECK-LABEL: test_svhadd_s32_x
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.shadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_s32_x'}}
+ return SVE_ACLE_FUNC(svhadd,_s32,_x,)(pg, op1, op2);
+}
+
+svint64_t test_svhadd_s64_x(svbool_t pg, svint64_t op1, svint64_t op2)
+{
+ // CHECK-LABEL: test_svhadd_s64_x
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.shadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_s64_x'}}
+ return SVE_ACLE_FUNC(svhadd,_s64,_x,)(pg, op1, op2);
+}
+
+svuint8_t test_svhadd_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2)
+{
+ // CHECK-LABEL: test_svhadd_u8_x
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uhadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_u8_x'}}
+ return SVE_ACLE_FUNC(svhadd,_u8,_x,)(pg, op1, op2);
+}
+
+svuint16_t test_svhadd_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2)
+{
+ // CHECK-LABEL: test_svhadd_u16_x
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uhadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_u16_x'}}
+ return SVE_ACLE_FUNC(svhadd,_u16,_x,)(pg, op1, op2);
+}
+
+svuint32_t test_svhadd_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2)
+{
+ // CHECKA-LABEL: test_svhadd_u32_x
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uhadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_u32_x'}}
+ return SVE_ACLE_FUNC(svhadd,_u32,_x,)(pg, op1, op2);
+}
+
+svuint64_t test_svhadd_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2)
+{
+ // CHECK-LABEL: test_svhadd_u64_x
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uhadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_u64_x'}}
+ return SVE_ACLE_FUNC(svhadd,_u64,_x,)(pg, op1, op2);
+}
+
+svint8_t test_svhadd_n_s8_x(svbool_t pg, svint8_t op1, int8_t op2)
+{
+ // CHECK-LABEL: test_svhadd_n_s8_x
+ // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.shadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_n_s8_x'}}
+ return SVE_ACLE_FUNC(svhadd,_n_s8,_x,)(pg, op1, op2);
+}
+
+svint16_t test_svhadd_n_s16_x(svbool_t pg, svint16_t op1, int16_t op2)
+{
+ // CHECK-LABEL: test_svhadd_n_s16_x
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.shadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_n_s16_x'}}
+ return SVE_ACLE_FUNC(svhadd,_n_s16,_x,)(pg, op1, op2);
+}
+
+svint32_t test_svhadd_n_s32_x(svbool_t pg, svint32_t op1, int32_t op2)
+{
+ // CHECK-LABEL: test_svhadd_n_s32_x
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.shadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_n_s32_x'}}
+ return SVE_ACLE_FUNC(svhadd,_n_s32,_x,)(pg, op1, op2);
+}
+
+svint64_t test_svhadd_n_s64_x(svbool_t pg, svint64_t op1, int64_t op2)
+{
+ // CHECK-LABEL: test_svhadd_n_s64_x
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.shadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_n_s64_x'}}
+ return SVE_ACLE_FUNC(svhadd,_n_s64,_x,)(pg, op1, op2);
+}
+
+svuint8_t test_svhadd_n_u8_x(svbool_t pg, svuint8_t op1, uint8_t op2)
+{
+ // CHECK-LABEL: test_svhadd_n_u8_x
+ // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uhadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_n_u8_x'}}
+ return SVE_ACLE_FUNC(svhadd,_n_u8,_x,)(pg, op1, op2);
+}
+
+svuint16_t test_svhadd_n_u16_x(svbool_t pg, svuint16_t op1, uint16_t op2)
+{
+ // CHECK-LABEL: test_svhadd_n_u16_x
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uhadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_n_u16_x'}}
+ return SVE_ACLE_FUNC(svhadd,_n_u16,_x,)(pg, op1, op2);
+}
+
+svuint32_t test_svhadd_n_u32_x(svbool_t pg, svuint32_t op1, uint32_t op2)
+{
+ // CHECK-LABEL: test_svhadd_n_u32_x
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uhadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_n_u32_x'}}
+ return SVE_ACLE_FUNC(svhadd,_n_u32,_x,)(pg, op1, op2);
+}
+
+svuint64_t test_svhadd_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2)
+{
+ // CHECK-LABEL: test_svhadd_n_u64_x
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uhadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhadd_n_u64_x'}}
+ return SVE_ACLE_FUNC(svhadd,_n_u64,_x,)(pg, op1, op2);
+}
diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_hsub.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_hsub.c
new file mode 100644
index 000000000000..386bae82e07b
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_hsub.c
@@ -0,0 +1,569 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s
+
+#include <arm_sve.h>
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+svint8_t test_svhsub_s8_z(svbool_t pg, svint8_t op1, svint8_t op2)
+{
+ // CHECK-LABEL: test_svhsub_s8_z
+ // CHECK: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.shsub.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_s8_z'}}
+ return SVE_ACLE_FUNC(svhsub,_s8,_z,)(pg, op1, op2);
+}
+
+svint16_t test_svhsub_s16_z(svbool_t pg, svint16_t op1, svint16_t op2)
+{
+ // CHECK-LABEL: test_svhsub_s16_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.shsub.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_s16_z'}}
+ return SVE_ACLE_FUNC(svhsub,_s16,_z,)(pg, op1, op2);
+}
+
+svint32_t test_svhsub_s32_z(svbool_t pg, svint32_t op1, svint32_t op2)
+{
+ // CHECK-LABEL: test_svhsub_s32_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.shsub.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_s32_z'}}
+ return SVE_ACLE_FUNC(svhsub,_s32,_z,)(pg, op1, op2);
+}
+
+svint64_t test_svhsub_s64_z(svbool_t pg, svint64_t op1, svint64_t op2)
+{
+ // CHECK-LABEL: test_svhsub_s64_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.shsub.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_s64_z'}}
+ return SVE_ACLE_FUNC(svhsub,_s64,_z,)(pg, op1, op2);
+}
+
+svuint8_t test_svhsub_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2)
+{
+ // CHECK-LABEL: test_svhsub_u8_z
+ // CHECK: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uhsub.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_u8_z'}}
+ return SVE_ACLE_FUNC(svhsub,_u8,_z,)(pg, op1, op2);
+}
+
+svuint16_t test_svhsub_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2)
+{
+ // CHECK-LABEL: test_svhsub_u16_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uhsub.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_u16_z'}}
+ return SVE_ACLE_FUNC(svhsub,_u16,_z,)(pg, op1, op2);
+}
+
+svuint32_t test_svhsub_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2)
+{
+ // CHECK-LABEL: test_svhsub_u32_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uhsub.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_u32_z'}}
+ return SVE_ACLE_FUNC(svhsub,_u32,_z,)(pg, op1, op2);
+}
+
+svuint64_t test_svhsub_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2)
+{
+ // CHECK-LABEL: test_svhsub_u64_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uhsub.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_u64_z'}}
+ return SVE_ACLE_FUNC(svhsub,_u64,_z,)(pg, op1, op2);
+}
+
+svint8_t test_svhsub_s8_m(svbool_t pg, svint8_t op1, svint8_t op2)
+{
+ // CHECK-LABEL: test_svhsub_s8_m
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.shsub.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_s8_m'}}
+ return SVE_ACLE_FUNC(svhsub,_s8,_m,)(pg, op1, op2);
+}
+
+svint16_t test_svhsub_s16_m(svbool_t pg, svint16_t op1, svint16_t op2)
+{
+ // CHECK-LABEL: test_svhsub_s16_m
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.shsub.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_s16_m'}}
+ return SVE_ACLE_FUNC(svhsub,_s16,_m,)(pg, op1, op2);
+}
+
+svint32_t test_svhsub_s32_m(svbool_t pg, svint32_t op1, svint32_t op2)
+{
+ // CHECK-LABEL: test_svhsub_s32_m
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.shsub.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_s32_m'}}
+ return SVE_ACLE_FUNC(svhsub,_s32,_m,)(pg, op1, op2);
+}
+
+svint64_t test_svhsub_s64_m(svbool_t pg, svint64_t op1, svint64_t op2)
+{
+ // CHECK-LABEL: test_svhsub_s64_m
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.shsub.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_s64_m'}}
+ return SVE_ACLE_FUNC(svhsub,_s64,_m,)(pg, op1, op2);
+}
+
+svuint8_t test_svhsub_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2)
+{
+ // CHECK-LABEL: test_svhsub_u8_m
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uhsub.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_u8_m'}}
+ return SVE_ACLE_FUNC(svhsub,_u8,_m,)(pg, op1, op2);
+}
+
+svuint16_t test_svhsub_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2)
+{
+ // CHECK-LABEL: test_svhsub_u16_m
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uhsub.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_u16_m'}}
+ return SVE_ACLE_FUNC(svhsub,_u16,_m,)(pg, op1, op2);
+}
+
+svuint32_t test_svhsub_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2)
+{
+ // CHECK-LABEL: test_svhsub_u32_m
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uhsub.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_u32_m'}}
+ return SVE_ACLE_FUNC(svhsub,_u32,_m,)(pg, op1, op2);
+}
+
+svuint64_t test_svhsub_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2)
+{
+ // CHECK-LABEL: test_svhsub_u64_m
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uhsub.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_u64_m'}}
+ return SVE_ACLE_FUNC(svhsub,_u64,_m,)(pg, op1, op2);
+}
+
+svint8_t test_svhsub_s8_x(svbool_t pg, svint8_t op1, svint8_t op2)
+{
+ // CHECK-LABEL: test_svhsub_s8_x
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.shsub.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_s8_x'}}
+ return SVE_ACLE_FUNC(svhsub,_s8,_x,)(pg, op1, op2);
+}
+
+svint16_t test_svhsub_s16_x(svbool_t pg, svint16_t op1, svint16_t op2)
+{
+ // CHECK-LABEL: test_svhsub_s16_x
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.shsub.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_s16_x'}}
+ return SVE_ACLE_FUNC(svhsub,_s16,_x,)(pg, op1, op2);
+}
+
+svint32_t test_svhsub_s32_x(svbool_t pg, svint32_t op1, svint32_t op2)
+{
+ // CHECK-LABEL: test_svhsub_s32_x
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.shsub.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_s32_x'}}
+ return SVE_ACLE_FUNC(svhsub,_s32,_x,)(pg, op1, op2);
+}
+
+svint64_t test_svhsub_s64_x(svbool_t pg, svint64_t op1, svint64_t op2)
+{
+ // CHECK-LABEL: test_svhsub_s64_x
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.shsub.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_s64_x'}}
+ return SVE_ACLE_FUNC(svhsub,_s64,_x,)(pg, op1, op2);
+}
+
+svuint8_t test_svhsub_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2)
+{
+ // CHECK-LABEL: test_svhsub_u8_x
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uhsub.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_u8_x'}}
+ return SVE_ACLE_FUNC(svhsub,_u8,_x,)(pg, op1, op2);
+}
+
+svuint16_t test_svhsub_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2)
+{
+ // CHECK-LABEL: test_svhsub_u16_x
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uhsub.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_u16_x'}}
+ return SVE_ACLE_FUNC(svhsub,_u16,_x,)(pg, op1, op2);
+}
+
+svuint32_t test_svhsub_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2)
+{
+ // CHECK-LABEL: test_svhsub_u32_x
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uhsub.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_u32_x'}}
+ return SVE_ACLE_FUNC(svhsub,_u32,_x,)(pg, op1, op2);
+}
+
+svuint64_t test_svhsub_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2)
+{
+ // CHECK-LABEL: test_svhsub_u64_x
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uhsub.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_u64_x'}}
+ return SVE_ACLE_FUNC(svhsub,_u64,_x,)(pg, op1, op2);
+}
+
+svint8_t test_svhsub_n_s8_z(svbool_t pg, svint8_t op1, int8_t op2)
+{
+ // CHECK-LABEL: test_svhsub_n_s8_z
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.shsub.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_n_s8_z'}}
+ return SVE_ACLE_FUNC(svhsub,_n_s8,_z,)(pg, op1, op2);
+}
+
+svint16_t test_svhsub_n_s16_z(svbool_t pg, svint16_t op1, int16_t op2)
+{
+ // CHECK-LABEL: test_svhsub_n_s16_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.shsub.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_n_s16_z'}}
+ return SVE_ACLE_FUNC(svhsub,_n_s16,_z,)(pg, op1, op2);
+}
+
+svint32_t test_svhsub_n_s32_z(svbool_t pg, svint32_t op1, int32_t op2)
+{
+ // CHECK-LABEL: test_svhsub_n_s32_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.shsub.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_n_s32_z'}}
+ return SVE_ACLE_FUNC(svhsub,_n_s32,_z,)(pg, op1, op2);
+}
+
+svint64_t test_svhsub_n_s64_z(svbool_t pg, svint64_t op1, int64_t op2)
+{
+ // CHECK-LABEL: test_svhsub_n_s64_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.shsub.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_n_s64_z'}}
+ return SVE_ACLE_FUNC(svhsub,_n_s64,_z,)(pg, op1, op2);
+}
+
+svuint8_t test_svhsub_n_u8_z(svbool_t pg, svuint8_t op1, uint8_t op2)
+{
+ // CHECK-LABEL: test_svhsub_n_u8_z
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uhsub.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_n_u8_z'}}
+ return SVE_ACLE_FUNC(svhsub,_n_u8,_z,)(pg, op1, op2);
+}
+
+svuint16_t test_svhsub_n_u16_z(svbool_t pg, svuint16_t op1, uint16_t op2)
+{
+ // CHECK-LABEL: test_svhsub_n_u16_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uhsub.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_n_u16_z'}}
+ return SVE_ACLE_FUNC(svhsub,_n_u16,_z,)(pg, op1, op2);
+}
+
+svuint32_t test_svhsub_n_u32_z(svbool_t pg, svuint32_t op1, uint32_t op2)
+{
+ // CHECK-LABEL: test_svhsub_n_u32_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uhsub.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_n_u32_z'}}
+ return SVE_ACLE_FUNC(svhsub,_n_u32,_z,)(pg, op1, op2);
+}
+
+svuint64_t test_svhsub_n_u64_z(svbool_t pg, svuint64_t op1, uint64_t op2)
+{
+ // CHECK-LABEL: test_svhsub_n_u64_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uhsub.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_n_u64_z'}}
+ return SVE_ACLE_FUNC(svhsub,_n_u64,_z,)(pg, op1, op2);
+}
+
+svint8_t test_svhsub_n_s8_m(svbool_t pg, svint8_t op1, int8_t op2)
+{
+ // CHECK-LABEL: test_svhsub_n_s8_m
+ // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.shsub.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_n_s8_m'}}
+ return SVE_ACLE_FUNC(svhsub,_n_s8,_m,)(pg, op1, op2);
+}
+
+svint16_t test_svhsub_n_s16_m(svbool_t pg, svint16_t op1, int16_t op2)
+{
+ // CHECK-LABEL: test_svhsub_n_s16_m
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.shsub.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_n_s16_m'}}
+ return SVE_ACLE_FUNC(svhsub,_n_s16,_m,)(pg, op1, op2);
+}
+
+svint32_t test_svhsub_n_s32_m(svbool_t pg, svint32_t op1, int32_t op2)
+{
+ // CHECK-LABEL: test_svhsub_n_s32_m
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.shsub.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_n_s32_m'}}
+ return SVE_ACLE_FUNC(svhsub,_n_s32,_m,)(pg, op1, op2);
+}
+
+svint64_t test_svhsub_n_s64_m(svbool_t pg, svint64_t op1, int64_t op2)
+{
+ // CHECK-LABEL: test_svhsub_n_s64_m
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.shsub.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_n_s64_m'}}
+ return SVE_ACLE_FUNC(svhsub,_n_s64,_m,)(pg, op1, op2);
+}
+
+svuint8_t test_svhsub_n_u8_m(svbool_t pg, svuint8_t op1, uint8_t op2)
+{
+ // CHECK-LABEL: test_svhsub_n_u8_m
+ // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uhsub.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_n_u8_m'}}
+ return SVE_ACLE_FUNC(svhsub,_n_u8,_m,)(pg, op1, op2);
+}
+
+svuint16_t test_svhsub_n_u16_m(svbool_t pg, svuint16_t op1, uint16_t op2)
+{
+ // CHECK-LABEL: test_svhsub_n_u16_m
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uhsub.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_n_u16_m'}}
+ return SVE_ACLE_FUNC(svhsub,_n_u16,_m,)(pg, op1, op2);
+}
+
+svuint32_t test_svhsub_n_u32_m(svbool_t pg, svuint32_t op1, uint32_t op2)
+{
+ // CHECK-LABEL: test_svhsub_n_u32_m
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uhsub.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_n_u32_m'}}
+ return SVE_ACLE_FUNC(svhsub,_n_u32,_m,)(pg, op1, op2);
+}
+
+svuint64_t test_svhsub_n_u64_m(svbool_t pg, svuint64_t op1, uint64_t op2)
+{
+ // CHECK-LABEL: test_svhsub_n_u64_m
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uhsub.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_n_u64_m'}}
+ return SVE_ACLE_FUNC(svhsub,_n_u64,_m,)(pg, op1, op2);
+}
+
+svint8_t test_svhsub_n_s8_x(svbool_t pg, svint8_t op1, int8_t op2)
+{
+ // CHECK-LABEL: test_svhsub_n_s8_x
+ // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.shsub.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_n_s8_x'}}
+ return SVE_ACLE_FUNC(svhsub,_n_s8,_x,)(pg, op1, op2);
+}
+
+svint16_t test_svhsub_n_s16_x(svbool_t pg, svint16_t op1, int16_t op2)
+{
+ // CHECK-LABEL: test_svhsub_n_s16_x
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.shsub.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_n_s16_x'}}
+ return SVE_ACLE_FUNC(svhsub,_n_s16,_x,)(pg, op1, op2);
+}
+
+svint32_t test_svhsub_n_s32_x(svbool_t pg, svint32_t op1, int32_t op2)
+{
+ // CHECK-LABEL: test_svhsub_n_s32_x
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.shsub.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_n_s32_x'}}
+ return SVE_ACLE_FUNC(svhsub,_n_s32,_x,)(pg, op1, op2);
+}
+
+svint64_t test_svhsub_n_s64_x(svbool_t pg, svint64_t op1, int64_t op2)
+{
+ // CHECK-LABEL: test_svhsub_n_s64_x
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.shsub.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_n_s64_x'}}
+ return SVE_ACLE_FUNC(svhsub,_n_s64,_x,)(pg, op1, op2);
+}
+
+svuint8_t test_svhsub_n_u8_x(svbool_t pg, svuint8_t op1, uint8_t op2)
+{
+ // CHECK-LABEL: test_svhsub_n_u8_x
+ // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uhsub.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_n_u8_x'}}
+ return SVE_ACLE_FUNC(svhsub,_n_u8,_x,)(pg, op1, op2);
+}
+
+svuint16_t test_svhsub_n_u16_x(svbool_t pg, svuint16_t op1, uint16_t op2)
+{
+ // CHECK-LABEL: test_svhsub_n_u16_x
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uhsub.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_n_u16_x'}}
+ return SVE_ACLE_FUNC(svhsub,_n_u16,_x,)(pg, op1, op2);
+}
+
+svuint32_t test_svhsub_n_u32_x(svbool_t pg, svuint32_t op1, uint32_t op2)
+{
+ // CHECK-LABEL: test_svhsub_n_u32_x
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uhsub.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_n_u32_x'}}
+ return SVE_ACLE_FUNC(svhsub,_n_u32,_x,)(pg, op1, op2);
+}
+
+svuint64_t test_svhsub_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2)
+{
+ // CHECK-LABEL: test_svhsub_n_u64_x
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uhsub.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsub_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsub_n_u64_x'}}
+ return SVE_ACLE_FUNC(svhsub,_n_u64,_x,)(pg, op1, op2);
+}
diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_hsubr.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_hsubr.c
new file mode 100644
index 000000000000..efc1544c6e3a
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_hsubr.c
@@ -0,0 +1,568 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s
+
+#include <arm_sve.h>
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+svint8_t test_svhsubr_s8_z(svbool_t pg, svint8_t op1, svint8_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_s8_z
+ // CHECK: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.shsubr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_s8_z'}}
+ return SVE_ACLE_FUNC(svhsubr,_s8,_z,)(pg, op1, op2);
+}
+
+svint16_t test_svhsubr_s16_z(svbool_t pg, svint16_t op1, svint16_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_s16_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.shsubr.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_s16_z'}}
+ return SVE_ACLE_FUNC(svhsubr,_s16,_z,)(pg, op1, op2);
+}
+
+svint32_t test_svhsubr_s32_z(svbool_t pg, svint32_t op1, svint32_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_s32_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.shsubr.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_s32_z'}}
+ return SVE_ACLE_FUNC(svhsubr,_s32,_z,)(pg, op1, op2);
+}
+
+svint64_t test_svhsubr_s64_z(svbool_t pg, svint64_t op1, svint64_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_s64_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.shsubr.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_s64_z'}}
+ return SVE_ACLE_FUNC(svhsubr,_s64,_z,)(pg, op1, op2);
+}
+
+svuint8_t test_svhsubr_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_u8_z
+ // CHECK: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uhsubr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_u8_z'}}
+ return SVE_ACLE_FUNC(svhsubr,_u8,_z,)(pg, op1, op2);
+}
+
+svuint16_t test_svhsubr_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_u16_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uhsubr.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_u16_z'}}
+ return SVE_ACLE_FUNC(svhsubr,_u16,_z,)(pg, op1, op2);
+}
+
+svuint32_t test_svhsubr_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_u32_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uhsubr.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_u32_z'}}
+ return SVE_ACLE_FUNC(svhsubr,_u32,_z,)(pg, op1, op2);
+}
+
+svuint64_t test_svhsubr_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_u64_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uhsubr.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_u64_z'}}
+ return SVE_ACLE_FUNC(svhsubr,_u64,_z,)(pg, op1, op2);
+}
+
+svint8_t test_svhsubr_s8_m(svbool_t pg, svint8_t op1, svint8_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_s8_m
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.shsubr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_s8_m'}}
+ return SVE_ACLE_FUNC(svhsubr,_s8,_m,)(pg, op1, op2);
+}
+
+svint16_t test_svhsubr_s16_m(svbool_t pg, svint16_t op1, svint16_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_s16_m
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.shsubr.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_s16_m'}}
+ return SVE_ACLE_FUNC(svhsubr,_s16,_m,)(pg, op1, op2);
+}
+
+svint32_t test_svhsubr_s32_m(svbool_t pg, svint32_t op1, svint32_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_s32_m
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.shsubr.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_s32_m'}}
+ return SVE_ACLE_FUNC(svhsubr,_s32,_m,)(pg, op1, op2);
+}
+
+svint64_t test_svhsubr_s64_m(svbool_t pg, svint64_t op1, svint64_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_s64_m
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.shsubr.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_s64_m'}}
+ return SVE_ACLE_FUNC(svhsubr,_s64,_m,)(pg, op1, op2);
+}
+
+svuint8_t test_svhsubr_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_u8_m
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uhsubr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_u8_m'}}
+ return SVE_ACLE_FUNC(svhsubr,_u8,_m,)(pg, op1, op2);
+}
+
+svuint16_t test_svhsubr_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_u16_m
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uhsubr.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_u16_m'}}
+ return SVE_ACLE_FUNC(svhsubr,_u16,_m,)(pg, op1, op2);
+}
+
+svuint32_t test_svhsubr_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_u32_m
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uhsubr.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_u32_m'}}
+ return SVE_ACLE_FUNC(svhsubr,_u32,_m,)(pg, op1, op2);
+}
+
+svuint64_t test_svhsubr_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_u64_m
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uhsubr.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_u64_m'}}
+ return SVE_ACLE_FUNC(svhsubr,_u64,_m,)(pg, op1, op2);
+}
+
+svint8_t test_svhsubr_s8_x(svbool_t pg, svint8_t op1, svint8_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_s8_x
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.shsubr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_s8_x'}}
+ return SVE_ACLE_FUNC(svhsubr,_s8,_x,)(pg, op1, op2);
+}
+
+svint16_t test_svhsubr_s16_x(svbool_t pg, svint16_t op1, svint16_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_s16_x
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.shsubr.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_s16_x'}}
+ return SVE_ACLE_FUNC(svhsubr,_s16,_x,)(pg, op1, op2);
+}
+
+svint32_t test_svhsubr_s32_x(svbool_t pg, svint32_t op1, svint32_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_s32_x
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.shsubr.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_s32_x'}}
+ return SVE_ACLE_FUNC(svhsubr,_s32,_x,)(pg, op1, op2);
+}
+
+svint64_t test_svhsubr_s64_x(svbool_t pg, svint64_t op1, svint64_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_s64_x
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.shsubr.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_s64_x'}}
+ return SVE_ACLE_FUNC(svhsubr,_s64,_x,)(pg, op1, op2);
+}
+
+svuint8_t test_svhsubr_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_u8_x
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uhsubr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_u8_x'}}
+ return SVE_ACLE_FUNC(svhsubr,_u8,_x,)(pg, op1, op2);
+}
+
+svuint16_t test_svhsubr_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_u16_x
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uhsubr.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_u16_x'}}
+ return SVE_ACLE_FUNC(svhsubr,_u16,_x,)(pg, op1, op2);
+}
+
+svuint32_t test_svhsubr_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_u32_x
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uhsubr.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_u32_x'}}
+ return SVE_ACLE_FUNC(svhsubr,_u32,_x,)(pg, op1, op2);
+}
+
+svuint64_t test_svhsubr_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_u64_x
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uhsubr.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_u64_x'}}
+ return SVE_ACLE_FUNC(svhsubr,_u64,_x,)(pg, op1, op2);
+}
+
+svint8_t test_svhsubr_n_s8_z(svbool_t pg, svint8_t op1, int8_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_n_s8_z
+ // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.shsubr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_n_s8_z'}}
+ return SVE_ACLE_FUNC(svhsubr,_n_s8,_z,)(pg, op1, op2);
+}
+
+svint16_t test_svhsubr_n_s16_z(svbool_t pg, svint16_t op1, int16_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_n_s16_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.shsubr.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_n_s16_z'}}
+ return SVE_ACLE_FUNC(svhsubr,_n_s16,_z,)(pg, op1, op2);
+}
+
+svint32_t test_svhsubr_n_s32_z(svbool_t pg, svint32_t op1, int32_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_n_s32_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.shsubr.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_n_s32_z'}}
+ return SVE_ACLE_FUNC(svhsubr,_n_s32,_z,)(pg, op1, op2);
+}
+
+svint64_t test_svhsubr_n_s64_z(svbool_t pg, svint64_t op1, int64_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_n_s64_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.shsubr.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_n_s64_z'}}
+ return SVE_ACLE_FUNC(svhsubr,_n_s64,_z,)(pg, op1, op2);
+}
+
+svuint8_t test_svhsubr_n_u8_z(svbool_t pg, svuint8_t op1, uint8_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_n_u8_z
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uhsubr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_n_u8_z'}}
+ return SVE_ACLE_FUNC(svhsubr,_n_u8,_z,)(pg, op1, op2);
+}
+
+svuint16_t test_svhsubr_n_u16_z(svbool_t pg, svuint16_t op1, uint16_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_n_u16_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uhsubr.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_n_u16_z'}}
+ return SVE_ACLE_FUNC(svhsubr,_n_u16,_z,)(pg, op1, op2);
+}
+
+svuint32_t test_svhsubr_n_u32_z(svbool_t pg, svuint32_t op1, uint32_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_n_u32_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uhsubr.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_n_u32_z'}}
+ return SVE_ACLE_FUNC(svhsubr,_n_u32,_z,)(pg, op1, op2);
+}
+
+svuint64_t test_svhsubr_n_u64_z(svbool_t pg, svuint64_t op1, uint64_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_n_u64_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uhsubr.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_n_u64_z'}}
+ return SVE_ACLE_FUNC(svhsubr,_n_u64,_z,)(pg, op1, op2);
+}
+
+svint8_t test_svhsubr_n_s8_m(svbool_t pg, svint8_t op1, int8_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_n_s8_m
+ // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.shsubr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_n_s8_m'}}
+ return SVE_ACLE_FUNC(svhsubr,_n_s8,_m,)(pg, op1, op2);
+}
+
+svint16_t test_svhsubr_n_s16_m(svbool_t pg, svint16_t op1, int16_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_n_s16_m
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.shsubr.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_n_s16_m'}}
+ return SVE_ACLE_FUNC(svhsubr,_n_s16,_m,)(pg, op1, op2);
+}
+
+svint32_t test_svhsubr_n_s32_m(svbool_t pg, svint32_t op1, int32_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_n_s32_m
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.shsubr.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_n_s32_m'}}
+ return SVE_ACLE_FUNC(svhsubr,_n_s32,_m,)(pg, op1, op2);
+}
+
+svint64_t test_svhsubr_n_s64_m(svbool_t pg, svint64_t op1, int64_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_n_s64_m
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.shsubr.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_n_s64_m'}}
+ return SVE_ACLE_FUNC(svhsubr,_n_s64,_m,)(pg, op1, op2);
+}
+
+svuint8_t test_svhsubr_n_u8_m(svbool_t pg, svuint8_t op1, uint8_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_n_u8_m
+ // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uhsubr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_n_u8_m'}}
+ return SVE_ACLE_FUNC(svhsubr,_n_u8,_m,)(pg, op1, op2);
+}
+
+svuint16_t test_svhsubr_n_u16_m(svbool_t pg, svuint16_t op1, uint16_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_n_u16_m
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uhsubr.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_n_u16_m'}}
+ return SVE_ACLE_FUNC(svhsubr,_n_u16,_m,)(pg, op1, op2);
+}
+
+svuint32_t test_svhsubr_n_u32_m(svbool_t pg, svuint32_t op1, uint32_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_n_u32_m
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uhsubr.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_n_u32_m'}}
+ return SVE_ACLE_FUNC(svhsubr,_n_u32,_m,)(pg, op1, op2);
+}
+
+svuint64_t test_svhsubr_n_u64_m(svbool_t pg, svuint64_t op1, uint64_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_n_u64_m
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uhsubr.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_n_u64_m'}}
+ return SVE_ACLE_FUNC(svhsubr,_n_u64,_m,)(pg, op1, op2);
+}
+
+svint8_t test_svhsubr_n_s8_x(svbool_t pg, svint8_t op1, int8_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_n_s8_x
+ // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.shsubr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_n_s8_x'}}
+ return SVE_ACLE_FUNC(svhsubr,_n_s8,_x,)(pg, op1, op2);
+}
+
+svint16_t test_svhsubr_n_s16_x(svbool_t pg, svint16_t op1, int16_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_n_s16_x
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.shsubr.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_n_s16_x'}}
+ return SVE_ACLE_FUNC(svhsubr,_n_s16,_x,)(pg, op1, op2);
+}
+
+svint32_t test_svhsubr_n_s32_x(svbool_t pg, svint32_t op1, int32_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_n_s32_x
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.shsubr.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_n_s32_x'}}
+ return SVE_ACLE_FUNC(svhsubr,_n_s32,_x,)(pg, op1, op2);
+}
+
+svint64_t test_svhsubr_n_s64_x(svbool_t pg, svint64_t op1, int64_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_n_s64_x
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.shsubr.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_n_s64_x'}}
+ return SVE_ACLE_FUNC(svhsubr,_n_s64,_x,)(pg, op1, op2);
+}
+
+svuint8_t test_svhsubr_n_u8_x(svbool_t pg, svuint8_t op1, uint8_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_n_u8_x
+ // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uhsubr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_n_u8_x'}}
+ return SVE_ACLE_FUNC(svhsubr,_n_u8,_x,)(pg, op1, op2);
+}
+
+svuint16_t test_svhsubr_n_u16_x(svbool_t pg, svuint16_t op1, uint16_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_n_u16_x
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uhsubr.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_n_u16_x'}}
+ return SVE_ACLE_FUNC(svhsubr,_n_u16,_x,)(pg, op1, op2);
+}
+
+svuint32_t test_svhsubr_n_u32_x(svbool_t pg, svuint32_t op1, uint32_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_n_u32_x
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uhsubr.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_n_u32_x'}}
+ return SVE_ACLE_FUNC(svhsubr,_n_u32,_x,)(pg, op1, op2);
+}
+
+svuint64_t test_svhsubr_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2)
+{
+ // CHECK-LABEL: test_svhsubr_n_u64_x
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uhsubr.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svhsubr_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svhsubr_n_u64_x'}}
+ return SVE_ACLE_FUNC(svhsubr,_n_u64,_x,)(pg, op1, op2);
+}
diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qabs.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qabs.c
new file mode 100644
index 000000000000..94442807d49c
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qabs.c
@@ -0,0 +1,142 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s
+
+#include <arm_sve.h>
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+svint8_t test_svqabs_s8_z(svbool_t pg, svint8_t op)
+{
+ // CHECK-LABEL: test_svqabs_s8_z
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sqabs.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqabs_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqabs_s8_z'}}
+ return SVE_ACLE_FUNC(svqabs,_s8,_z,)(pg, op);
+}
+
+svint16_t test_svqabs_s16_z(svbool_t pg, svint16_t op)
+{
+ // CHECK-LABEL: test_svqabs_s16_z
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sqabs.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqabs_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqabs_s16_z'}}
+ return SVE_ACLE_FUNC(svqabs,_s16,_z,)(pg, op);
+}
+
+svint32_t test_svqabs_s32_z(svbool_t pg, svint32_t op)
+{
+ // CHECK-LABEL: test_svqabs_s32_z
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sqabs.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqabs_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqabs_s32_z'}}
+ return SVE_ACLE_FUNC(svqabs,_s32,_z,)(pg, op);
+}
+
+svint64_t test_svqabs_s64_z(svbool_t pg, svint64_t op)
+{
+ // CHECK-LABEL: test_svqabs_s64_z
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sqabs.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqabs_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqabs_s64_z'}}
+ return SVE_ACLE_FUNC(svqabs,_s64,_z,)(pg, op);
+}
+
+svint8_t test_svqabs_s8_m(svint8_t inactive, svbool_t pg, svint8_t op)
+{
+ // CHECK-LABEL: test_svqabs_s8_m
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sqabs.nxv16i8(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqabs_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqabs_s8_m'}}
+ return SVE_ACLE_FUNC(svqabs,_s8,_m,)(inactive, pg, op);
+}
+
+svint16_t test_svqabs_s16_m(svint16_t inactive, svbool_t pg, svint16_t op)
+{
+ // CHECK-LABEL: test_svqabs_s16_m
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sqabs.nxv8i16(<vscale x 8 x i16> %inactive, <vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqabs_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqabs_s16_m'}}
+ return SVE_ACLE_FUNC(svqabs,_s16,_m,)(inactive, pg, op);
+}
+
+svint32_t test_svqabs_s32_m(svint32_t inactive, svbool_t pg, svint32_t op)
+{
+ // CHECK-LABEL: test_svqabs_s32_m
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sqabs.nxv4i32(<vscale x 4 x i32> %inactive, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqabs_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqabs_s32_m'}}
+ return SVE_ACLE_FUNC(svqabs,_s32,_m,)(inactive, pg, op);
+}
+
+svint64_t test_svqabs_s64_m(svint64_t inactive, svbool_t pg, svint64_t op)
+{
+ // CHECK-LABEL: test_svqabs_s64_m
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sqabs.nxv2i64(<vscale x 2 x i64> %inactive, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqabs_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqabs_s64_m'}}
+ return SVE_ACLE_FUNC(svqabs,_s64,_m,)(inactive, pg, op);
+}
+
+svint8_t test_svqabs_s8_x(svbool_t pg, svint8_t op)
+{
+ // CHECK-LABEL: test_svqabs_s8_x
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sqabs.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqabs_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqabs_s8_x'}}
+ return SVE_ACLE_FUNC(svqabs,_s8,_x,)(pg, op);
+}
+
+svint16_t test_svqabs_s16_x(svbool_t pg, svint16_t op)
+{
+ // CHECK-LABEL: test_svqabs_s16_x
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sqabs.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqabs_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqabs_s16_x'}}
+ return SVE_ACLE_FUNC(svqabs,_s16,_x,)(pg, op);
+}
+
+svint32_t test_svqabs_s32_x(svbool_t pg, svint32_t op)
+{
+ // CHECK-LABEL: test_svqabs_s32_x
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sqabs.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqabs_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqabs_s32_x'}}
+ return SVE_ACLE_FUNC(svqabs,_s32,_x,)(pg, op);
+}
+
+svint64_t test_svqabs_s64_x(svbool_t pg, svint64_t op)
+{
+ // CHECK-LABEL: test_svqabs_s64_x
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sqabs.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqabs_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqabs_s64_x'}}
+ return SVE_ACLE_FUNC(svqabs,_s64,_x,)(pg, op);
+}
diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qadd.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qadd.c
new file mode 100644
index 000000000000..2c035b6a77d0
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qadd.c
@@ -0,0 +1,568 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s
+
+#include <arm_sve.h>
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+svint8_t test_svqadd_s8_m(svbool_t pg, svint8_t op1, svint8_t op2)
+{
+ // CHECK-LABEL: test_svqadd_s8_m
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sqadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_s8_m'}}
+ return SVE_ACLE_FUNC(svqadd,_s8,_m,)(pg, op1, op2);
+}
+
+svint16_t test_svqadd_s16_m(svbool_t pg, svint16_t op1, svint16_t op2)
+{
+ // CHECK-LABEL: test_svqadd_s16_m
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sqadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_s16_m'}}
+ return SVE_ACLE_FUNC(svqadd,_s16,_m,)(pg, op1, op2);
+}
+
+svint32_t test_svqadd_s32_m(svbool_t pg, svint32_t op1, svint32_t op2)
+{
+ // CHECK-LABEL: test_svqadd_s32_m
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_s32_m'}}
+ return SVE_ACLE_FUNC(svqadd,_s32,_m,)(pg, op1, op2);
+}
+
+svint64_t test_svqadd_s64_m(svbool_t pg, svint64_t op1, svint64_t op2)
+{
+ // CHECK-LABEL: test_svqadd_s64_m
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sqadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_s64_m'}}
+ return SVE_ACLE_FUNC(svqadd,_s64,_m,)(pg, op1, op2);
+}
+
+svuint8_t test_svqadd_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2)
+{
+ // CHECK-LABEL: test_svqadd_u8_m
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uqadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_u8_m'}}
+ return SVE_ACLE_FUNC(svqadd,_u8,_m,)(pg, op1, op2);
+}
+
+svuint16_t test_svqadd_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2)
+{
+ // CHECK-LABEL: test_svqadd_u16_m
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uqadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_u16_m'}}
+ return SVE_ACLE_FUNC(svqadd,_u16,_m,)(pg, op1, op2);
+}
+
+svuint32_t test_svqadd_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2)
+{
+ // CHECKA-LABEL: test_svqadd_u32_m
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uqadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_u32_m'}}
+ return SVE_ACLE_FUNC(svqadd,_u32,_m,)(pg, op1, op2);
+}
+
+svuint64_t test_svqadd_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2)
+{
+ // CHECK-LABEL: test_svqadd_u64_m
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uqadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_u64_m'}}
+ return SVE_ACLE_FUNC(svqadd,_u64,_m,)(pg, op1, op2);
+}
+
+svint8_t test_svqadd_n_s8_m(svbool_t pg, svint8_t op1, int8_t op2)
+{
+ // CHECK-LABEL: test_svqadd_n_s8_m
+ // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sqadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_n_s8_m'}}
+ return SVE_ACLE_FUNC(svqadd,_n_s8,_m,)(pg, op1, op2);
+}
+
+svint16_t test_svqadd_n_s16_m(svbool_t pg, svint16_t op1, int16_t op2)
+{
+ // CHECK-LABEL: test_svqadd_n_s16_m
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sqadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_n_s16_m'}}
+ return SVE_ACLE_FUNC(svqadd,_n_s16,_m,)(pg, op1, op2);
+}
+
+svint32_t test_svqadd_n_s32_m(svbool_t pg, svint32_t op1, int32_t op2)
+{
+ // CHECK-LABEL: test_svqadd_n_s32_m
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_n_s32_m'}}
+ return SVE_ACLE_FUNC(svqadd,_n_s32,_m,)(pg, op1, op2);
+}
+
+svint64_t test_svqadd_n_s64_m(svbool_t pg, svint64_t op1, int64_t op2)
+{
+ // CHECK-LABEL: test_svqadd_n_s64_m
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sqadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_n_s64_m'}}
+ return SVE_ACLE_FUNC(svqadd,_n_s64,_m,)(pg, op1, op2);
+}
+
+svuint8_t test_svqadd_n_u8_m(svbool_t pg, svuint8_t op1, uint8_t op2)
+{
+ // CHECK-LABEL: test_svqadd_n_u8_m
+ // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uqadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_n_u8_m'}}
+ return SVE_ACLE_FUNC(svqadd,_n_u8,_m,)(pg, op1, op2);
+}
+
+svuint16_t test_svqadd_n_u16_m(svbool_t pg, svuint16_t op1, uint16_t op2)
+{
+ // CHECK-LABEL: test_svqadd_n_u16_m
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uqadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_n_u16_m'}}
+ return SVE_ACLE_FUNC(svqadd,_n_u16,_m,)(pg, op1, op2);
+}
+
+svuint32_t test_svqadd_n_u32_m(svbool_t pg, svuint32_t op1, uint32_t op2)
+{
+ // CHECK-LABEL: test_svqadd_n_u32_m
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uqadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_n_u32_m'}}
+ return SVE_ACLE_FUNC(svqadd,_n_u32,_m,)(pg, op1, op2);
+}
+
+svuint64_t test_svqadd_n_u64_m(svbool_t pg, svuint64_t op1, uint64_t op2)
+{
+ // CHECK-LABEL: test_svqadd_n_u64_m
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uqadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_n_u64_m'}}
+ return SVE_ACLE_FUNC(svqadd,_n_u64,_m,)(pg, op1, op2);
+}
+
+svint8_t test_svqadd_s8_z(svbool_t pg, svint8_t op1, svint8_t op2)
+{
+ // CHECK-LABEL: test_svqadd_s8_z
+ // CHECK: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sqadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_s8_z'}}
+ return SVE_ACLE_FUNC(svqadd,_s8,_z,)(pg, op1, op2);
+}
+
+svint16_t test_svqadd_s16_z(svbool_t pg, svint16_t op1, svint16_t op2)
+{
+ // CHECK-LABEL: test_svqadd_s16_z
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sqadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_s16_z'}}
+ return SVE_ACLE_FUNC(svqadd,_s16,_z,)(pg, op1, op2);
+}
+
+svint32_t test_svqadd_s32_z(svbool_t pg, svint32_t op1, svint32_t op2)
+{
+ // CHECK-LABEL: test_svqadd_s32_z
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_s32_z'}}
+ return SVE_ACLE_FUNC(svqadd,_s32,_z,)(pg, op1, op2);
+}
+
+svint64_t test_svqadd_s64_z(svbool_t pg, svint64_t op1, svint64_t op2)
+{
+ // CHECK-LABEL: test_svqadd_s64_z
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sqadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_s64_z'}}
+ return SVE_ACLE_FUNC(svqadd,_s64,_z,)(pg, op1, op2);
+}
+
+svuint8_t test_svqadd_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2)
+{
+ // CHECK-LABEL: test_svqadd_u8_z
+ // CHECK: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uqadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_u8_z'}}
+ return SVE_ACLE_FUNC(svqadd,_u8,_z,)(pg, op1, op2);
+}
+
+svuint16_t test_svqadd_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2)
+{
+ // CHECK-LABEL: test_svqadd_u16_z
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uqadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_u16_z'}}
+ return SVE_ACLE_FUNC(svqadd,_u16,_z,)(pg, op1, op2);
+}
+
+svuint32_t test_svqadd_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2)
+{
+ // CHECKA-LABEL: test_svqadd_u32_z
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uqadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_u32_z'}}
+ return SVE_ACLE_FUNC(svqadd,_u32,_z,)(pg, op1, op2);
+}
+
+svuint64_t test_svqadd_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2)
+{
+ // CHECK-LABEL: test_svqadd_u64_z
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uqadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_u64_z'}}
+ return SVE_ACLE_FUNC(svqadd,_u64,_z,)(pg, op1, op2);
+}
+
+svint8_t test_svqadd_n_s8_z(svbool_t pg, svint8_t op1, int8_t op2)
+{
+ // CHECK-LABEL: test_svqadd_n_s8_z
+ // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sqadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_n_s8_z'}}
+ return SVE_ACLE_FUNC(svqadd,_n_s8,_z,)(pg, op1, op2);
+}
+
+svint16_t test_svqadd_n_s16_z(svbool_t pg, svint16_t op1, int16_t op2)
+{
+ // CHECK-LABEL: test_svqadd_n_s16_z
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sqadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_n_s16_z'}}
+ return SVE_ACLE_FUNC(svqadd,_n_s16,_z,)(pg, op1, op2);
+}
+
+svint32_t test_svqadd_n_s32_z(svbool_t pg, svint32_t op1, int32_t op2)
+{
+ // CHECK-LABEL: test_svqadd_n_s32_z
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_n_s32_z'}}
+ return SVE_ACLE_FUNC(svqadd,_n_s32,_z,)(pg, op1, op2);
+}
+
+svint64_t test_svqadd_n_s64_z(svbool_t pg, svint64_t op1, int64_t op2)
+{
+ // CHECK-LABEL: test_svqadd_n_s64_z
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sqadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_n_s64_z'}}
+ return SVE_ACLE_FUNC(svqadd,_n_s64,_z,)(pg, op1, op2);
+}
+
+svuint8_t test_svqadd_n_u8_z(svbool_t pg, svuint8_t op1, uint8_t op2)
+{
+ // CHECK-LABEL: test_svqadd_n_u8_z
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uqadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_n_u8_z'}}
+ return SVE_ACLE_FUNC(svqadd,_n_u8,_z,)(pg, op1, op2);
+}
+
+svuint16_t test_svqadd_n_u16_z(svbool_t pg, svuint16_t op1, uint16_t op2)
+{
+ // CHECK-LABEL: test_svqadd_n_u16_z
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uqadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_n_u16_z'}}
+ return SVE_ACLE_FUNC(svqadd,_n_u16,_z,)(pg, op1, op2);
+}
+
+svuint32_t test_svqadd_n_u32_z(svbool_t pg, svuint32_t op1, uint32_t op2)
+{
+ // CHECK-LABEL: test_svqadd_n_u32_z
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uqadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_n_u32_z'}}
+ return SVE_ACLE_FUNC(svqadd,_n_u32,_z,)(pg, op1, op2);
+}
+
+svuint64_t test_svqadd_n_u64_z(svbool_t pg, svuint64_t op1, uint64_t op2)
+{
+ // CHECK-LABEL: test_svqadd_n_u64_z
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uqadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_n_u64_z'}}
+ return SVE_ACLE_FUNC(svqadd,_n_u64,_z,)(pg, op1, op2);
+}
+
+svint8_t test_svqadd_s8_x(svbool_t pg, svint8_t op1, svint8_t op2)
+{
+ // CHECK-LABEL: test_svqadd_s8_x
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sqadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_s8_x'}}
+ return SVE_ACLE_FUNC(svqadd,_s8,_x,)(pg, op1, op2);
+}
+
+svint16_t test_svqadd_s16_x(svbool_t pg, svint16_t op1, svint16_t op2)
+{
+ // CHECK-LABEL: test_svqadd_s16_x
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sqadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_s16_x'}}
+ return SVE_ACLE_FUNC(svqadd,_s16,_x,)(pg, op1, op2);
+}
+
+svint32_t test_svqadd_s32_x(svbool_t pg, svint32_t op1, svint32_t op2)
+{
+ // CHECK-LABEL: test_svqadd_s32_x
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_s32_x'}}
+ return SVE_ACLE_FUNC(svqadd,_s32,_x,)(pg, op1, op2);
+}
+
+svint64_t test_svqadd_s64_x(svbool_t pg, svint64_t op1, svint64_t op2)
+{
+ // CHECK-LABEL: test_svqadd_s64_x
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sqadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_s64_x'}}
+ return SVE_ACLE_FUNC(svqadd,_s64,_x,)(pg, op1, op2);
+}
+
+svuint8_t test_svqadd_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2)
+{
+ // CHECK-LABEL: test_svqadd_u8_x
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uqadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_u8_x'}}
+ return SVE_ACLE_FUNC(svqadd,_u8,_x,)(pg, op1, op2);
+}
+
+svuint16_t test_svqadd_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2)
+{
+ // CHECK-LABEL: test_svqadd_u16_x
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uqadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_u16_x'}}
+ return SVE_ACLE_FUNC(svqadd,_u16,_x,)(pg, op1, op2);
+}
+
+svuint32_t test_svqadd_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2)
+{
+ // CHECKA-LABEL: test_svqadd_u32_x
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uqadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_u32_x'}}
+ return SVE_ACLE_FUNC(svqadd,_u32,_x,)(pg, op1, op2);
+}
+
+svuint64_t test_svqadd_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2)
+{
+ // CHECK-LABEL: test_svqadd_u64_x
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uqadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_u64_x'}}
+ return SVE_ACLE_FUNC(svqadd,_u64,_x,)(pg, op1, op2);
+}
+
+svint8_t test_svqadd_n_s8_x(svbool_t pg, svint8_t op1, int8_t op2)
+{
+ // CHECK-LABEL: test_svqadd_n_s8_x
+ // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sqadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_n_s8_x'}}
+ return SVE_ACLE_FUNC(svqadd,_n_s8,_x,)(pg, op1, op2);
+}
+
+svint16_t test_svqadd_n_s16_x(svbool_t pg, svint16_t op1, int16_t op2)
+{
+ // CHECK-LABEL: test_svqadd_n_s16_x
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sqadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_n_s16_x'}}
+ return SVE_ACLE_FUNC(svqadd,_n_s16,_x,)(pg, op1, op2);
+}
+
+svint32_t test_svqadd_n_s32_x(svbool_t pg, svint32_t op1, int32_t op2)
+{
+ // CHECK-LABEL: test_svqadd_n_s32_x
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_n_s32_x'}}
+ return SVE_ACLE_FUNC(svqadd,_n_s32,_x,)(pg, op1, op2);
+}
+
+svint64_t test_svqadd_n_s64_x(svbool_t pg, svint64_t op1, int64_t op2)
+{
+ // CHECK-LABEL: test_svqadd_n_s64_x
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sqadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_n_s64_x'}}
+ return SVE_ACLE_FUNC(svqadd,_n_s64,_x,)(pg, op1, op2);
+}
+
+svuint8_t test_svqadd_n_u8_x(svbool_t pg, svuint8_t op1, uint8_t op2)
+{
+ // CHECK-LABEL: test_svqadd_n_u8_x
+ // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uqadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_n_u8_x'}}
+ return SVE_ACLE_FUNC(svqadd,_n_u8,_x,)(pg, op1, op2);
+}
+
+svuint16_t test_svqadd_n_u16_x(svbool_t pg, svuint16_t op1, uint16_t op2)
+{
+ // CHECK-LABEL: test_svqadd_n_u16_x
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uqadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_n_u16_x'}}
+ return SVE_ACLE_FUNC(svqadd,_n_u16,_x,)(pg, op1, op2);
+}
+
+svuint32_t test_svqadd_n_u32_x(svbool_t pg, svuint32_t op1, uint32_t op2)
+{
+ // CHECK-LABEL: test_svqadd_n_u32_x
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uqadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_n_u32_x'}}
+ return SVE_ACLE_FUNC(svqadd,_n_u32,_x,)(pg, op1, op2);
+}
+
+svuint64_t test_svqadd_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2)
+{
+ // CHECK-LABEL: test_svqadd_n_u64_x
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uqadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqadd_n_u64_x'}}
+ return SVE_ACLE_FUNC(svqadd,_n_u64,_x,)(pg, op1, op2);
+}
diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qneg.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qneg.c
new file mode 100644
index 000000000000..a734f741d780
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qneg.c
@@ -0,0 +1,142 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s
+
+#include <arm_sve.h>
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+svint8_t test_svqneg_s8_z(svbool_t pg, svint8_t op)
+{
+ // CHECK-LABEL: test_svqneg_s8_z
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sqneg.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqneg_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqneg_s8_z'}}
+ return SVE_ACLE_FUNC(svqneg,_s8,_z,)(pg, op);
+}
+
+svint16_t test_svqneg_s16_z(svbool_t pg, svint16_t op)
+{
+ // CHECK-LABEL: test_svqneg_s16_z
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sqneg.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqneg_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqneg_s16_z'}}
+ return SVE_ACLE_FUNC(svqneg,_s16,_z,)(pg, op);
+}
+
+svint32_t test_svqneg_s32_z(svbool_t pg, svint32_t op)
+{
+ // CHECK-LABEL: test_svqneg_s32_z
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sqneg.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqneg_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqneg_s32_z'}}
+ return SVE_ACLE_FUNC(svqneg,_s32,_z,)(pg, op);
+}
+
+svint64_t test_svqneg_s64_z(svbool_t pg, svint64_t op)
+{
+ // CHECK-LABEL: test_svqneg_s64_z
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sqneg.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqneg_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqneg_s64_z'}}
+ return SVE_ACLE_FUNC(svqneg,_s64,_z,)(pg, op);
+}
+
+svint8_t test_svqneg_s8_m(svint8_t inactive, svbool_t pg, svint8_t op)
+{
+ // CHECK-LABEL: test_svqneg_s8_m
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sqneg.nxv16i8(<vscale x 16 x i8> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqneg_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqneg_s8_m'}}
+ return SVE_ACLE_FUNC(svqneg,_s8,_m,)(inactive, pg, op);
+}
+
+svint16_t test_svqneg_s16_m(svint16_t inactive, svbool_t pg, svint16_t op)
+{
+ // CHECK-LABEL: test_svqneg_s16_m
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sqneg.nxv8i16(<vscale x 8 x i16> %inactive, <vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqneg_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqneg_s16_m'}}
+ return SVE_ACLE_FUNC(svqneg,_s16,_m,)(inactive, pg, op);
+}
+
+svint32_t test_svqneg_s32_m(svint32_t inactive, svbool_t pg, svint32_t op)
+{
+ // CHECK-LABEL: test_svqneg_s32_m
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sqneg.nxv4i32(<vscale x 4 x i32> %inactive, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqneg_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqneg_s32_m'}}
+ return SVE_ACLE_FUNC(svqneg,_s32,_m,)(inactive, pg, op);
+}
+
+svint64_t test_svqneg_s64_m(svint64_t inactive, svbool_t pg, svint64_t op)
+{
+ // CHECK-LABEL: test_svqneg_s64_m
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sqneg.nxv2i64(<vscale x 2 x i64> %inactive, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqneg_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqneg_s64_m'}}
+ return SVE_ACLE_FUNC(svqneg,_s64,_m,)(inactive, pg, op);
+}
+
+svint8_t test_svqneg_s8_x(svbool_t pg, svint8_t op)
+{
+ // CHECK-LABEL: test_svqneg_s8_x
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sqneg.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %op)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqneg_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqneg_s8_x'}}
+ return SVE_ACLE_FUNC(svqneg,_s8,_x,)(pg, op);
+}
+
+svint16_t test_svqneg_s16_x(svbool_t pg, svint16_t op)
+{
+ // CHECK-LABEL: test_svqneg_s16_x
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sqneg.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqneg_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqneg_s16_x'}}
+ return SVE_ACLE_FUNC(svqneg,_s16,_x,)(pg, op);
+}
+
+svint32_t test_svqneg_s32_x(svbool_t pg, svint32_t op)
+{
+ // CHECK-LABEL: test_svqneg_s32_x
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sqneg.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqneg_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqneg_s32_x'}}
+ return SVE_ACLE_FUNC(svqneg,_s32,_x,)(pg, op);
+}
+
+svint64_t test_svqneg_s64_x(svbool_t pg, svint64_t op)
+{
+ // CHECK-LABEL: test_svqneg_s64_x
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sqneg.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqneg_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqneg_s64_x'}}
+ return SVE_ACLE_FUNC(svqneg,_s64,_x,)(pg, op);
+}
diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qsub.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qsub.c
new file mode 100644
index 000000000000..63bbb8c0390e
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qsub.c
@@ -0,0 +1,569 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s
+
+#include <arm_sve.h>
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+svint8_t test_svqsub_s8_z(svbool_t pg, svint8_t op1, svint8_t op2)
+{
+ // CHECK-LABEL: test_svqsub_s8_z
+ // CHECK: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sqsub.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_s8_z'}}
+ return SVE_ACLE_FUNC(svqsub,_s8,_z,)(pg, op1, op2);
+}
+
+svint16_t test_svqsub_s16_z(svbool_t pg, svint16_t op1, svint16_t op2)
+{
+ // CHECK-LABEL: test_svqsub_s16_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_s16_z'}}
+ return SVE_ACLE_FUNC(svqsub,_s16,_z,)(pg, op1, op2);
+}
+
+svint32_t test_svqsub_s32_z(svbool_t pg, svint32_t op1, svint32_t op2)
+{
+ // CHECK-LABEL: test_svqsub_s32_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_s32_z'}}
+ return SVE_ACLE_FUNC(svqsub,_s32,_z,)(pg, op1, op2);
+}
+
+svint64_t test_svqsub_s64_z(svbool_t pg, svint64_t op1, svint64_t op2)
+{
+ // CHECK-LABEL: test_svqsub_s64_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_s64_z'}}
+ return SVE_ACLE_FUNC(svqsub,_s64,_z,)(pg, op1, op2);
+}
+
+svuint8_t test_svqsub_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2)
+{
+ // CHECK-LABEL: test_svqsub_u8_z
+ // CHECK: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uqsub.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_u8_z'}}
+ return SVE_ACLE_FUNC(svqsub,_u8,_z,)(pg, op1, op2);
+}
+
+svuint16_t test_svqsub_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2)
+{
+ // CHECK-LABEL: test_svqsub_u16_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uqsub.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_u16_z'}}
+ return SVE_ACLE_FUNC(svqsub,_u16,_z,)(pg, op1, op2);
+}
+
+svuint32_t test_svqsub_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2)
+{
+ // CHECK-LABEL: test_svqsub_u32_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uqsub.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_u32_z'}}
+ return SVE_ACLE_FUNC(svqsub,_u32,_z,)(pg, op1, op2);
+}
+
+svuint64_t test_svqsub_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2)
+{
+ // CHECK-LABEL: test_svqsub_u64_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uqsub.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_u64_z'}}
+ return SVE_ACLE_FUNC(svqsub,_u64,_z,)(pg, op1, op2);
+}
+
+svint8_t test_svqsub_s8_m(svbool_t pg, svint8_t op1, svint8_t op2)
+{
+ // CHECK-LABEL: test_svqsub_s8_m
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sqsub.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_s8_m'}}
+ return SVE_ACLE_FUNC(svqsub,_s8,_m,)(pg, op1, op2);
+}
+
+svint16_t test_svqsub_s16_m(svbool_t pg, svint16_t op1, svint16_t op2)
+{
+ // CHECK-LABEL: test_svqsub_s16_m
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_s16_m'}}
+ return SVE_ACLE_FUNC(svqsub,_s16,_m,)(pg, op1, op2);
+}
+
+svint32_t test_svqsub_s32_m(svbool_t pg, svint32_t op1, svint32_t op2)
+{
+ // CHECK-LABEL: test_svqsub_s32_m
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_s32_m'}}
+ return SVE_ACLE_FUNC(svqsub,_s32,_m,)(pg, op1, op2);
+}
+
+svint64_t test_svqsub_s64_m(svbool_t pg, svint64_t op1, svint64_t op2)
+{
+ // CHECK-LABEL: test_svqsub_s64_m
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_s64_m'}}
+ return SVE_ACLE_FUNC(svqsub,_s64,_m,)(pg, op1, op2);
+}
+
+svuint8_t test_svqsub_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2)
+{
+ // CHECK-LABEL: test_svqsub_u8_m
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uqsub.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_u8_m'}}
+ return SVE_ACLE_FUNC(svqsub,_u8,_m,)(pg, op1, op2);
+}
+
+svuint16_t test_svqsub_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2)
+{
+ // CHECK-LABEL: test_svqsub_u16_m
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uqsub.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_u16_m'}}
+ return SVE_ACLE_FUNC(svqsub,_u16,_m,)(pg, op1, op2);
+}
+
+svuint32_t test_svqsub_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2)
+{
+ // CHECK-LABEL: test_svqsub_u32_m
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uqsub.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_u32_m'}}
+ return SVE_ACLE_FUNC(svqsub,_u32,_m,)(pg, op1, op2);
+}
+
+svuint64_t test_svqsub_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2)
+{
+ // CHECK-LABEL: test_svqsub_u64_m
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uqsub.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_u64_m'}}
+ return SVE_ACLE_FUNC(svqsub,_u64,_m,)(pg, op1, op2);
+}
+
+svint8_t test_svqsub_s8_x(svbool_t pg, svint8_t op1, svint8_t op2)
+{
+ // CHECK-LABEL: test_svqsub_s8_x
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sqsub.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_s8_x'}}
+ return SVE_ACLE_FUNC(svqsub,_s8,_x,)(pg, op1, op2);
+}
+
+svint16_t test_svqsub_s16_x(svbool_t pg, svint16_t op1, svint16_t op2)
+{
+ // CHECK-LABEL: test_svqsub_s16_x
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_s16_x'}}
+ return SVE_ACLE_FUNC(svqsub,_s16,_x,)(pg, op1, op2);
+}
+
+svint32_t test_svqsub_s32_x(svbool_t pg, svint32_t op1, svint32_t op2)
+{
+ // CHECK-LABEL: test_svqsub_s32_x
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_s32_x'}}
+ return SVE_ACLE_FUNC(svqsub,_s32,_x,)(pg, op1, op2);
+}
+
+svint64_t test_svqsub_s64_x(svbool_t pg, svint64_t op1, svint64_t op2)
+{
+ // CHECK-LABEL: test_svqsub_s64_x
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_s64_x'}}
+ return SVE_ACLE_FUNC(svqsub,_s64,_x,)(pg, op1, op2);
+}
+
+svuint8_t test_svqsub_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2)
+{
+ // CHECK-LABEL: test_svqsub_u8_x
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uqsub.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_u8_x'}}
+ return SVE_ACLE_FUNC(svqsub,_u8,_x,)(pg, op1, op2);
+}
+
+svuint16_t test_svqsub_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2)
+{
+ // CHECK-LABEL: test_svqsub_u16_x
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uqsub.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_u16_x'}}
+ return SVE_ACLE_FUNC(svqsub,_u16,_x,)(pg, op1, op2);
+}
+
+svuint32_t test_svqsub_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2)
+{
+ // CHECK-LABEL: test_svqsub_u32_x
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uqsub.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_u32_x'}}
+ return SVE_ACLE_FUNC(svqsub,_u32,_x,)(pg, op1, op2);
+}
+
+svuint64_t test_svqsub_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2)
+{
+ // CHECK-LABEL: test_svqsub_u64_x
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uqsub.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_u64_x'}}
+ return SVE_ACLE_FUNC(svqsub,_u64,_x,)(pg, op1, op2);
+}
+
+svint8_t test_svqsub_n_s8_z(svbool_t pg, svint8_t op1, int8_t op2)
+{
+ // CHECK-LABEL: test_svqsub_n_s8_z
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sqsub.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_n_s8_z'}}
+ return SVE_ACLE_FUNC(svqsub,_n_s8,_z,)(pg, op1, op2);
+}
+
+svint16_t test_svqsub_n_s16_z(svbool_t pg, svint16_t op1, int16_t op2)
+{
+ // CHECK-LABEL: test_svqsub_n_s16_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_n_s16_z'}}
+ return SVE_ACLE_FUNC(svqsub,_n_s16,_z,)(pg, op1, op2);
+}
+
+svint32_t test_svqsub_n_s32_z(svbool_t pg, svint32_t op1, int32_t op2)
+{
+ // CHECK-LABEL: test_svqsub_n_s32_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_n_s32_z'}}
+ return SVE_ACLE_FUNC(svqsub,_n_s32,_z,)(pg, op1, op2);
+}
+
+svint64_t test_svqsub_n_s64_z(svbool_t pg, svint64_t op1, int64_t op2)
+{
+ // CHECK-LABEL: test_svqsub_n_s64_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_n_s64_z'}}
+ return SVE_ACLE_FUNC(svqsub,_n_s64,_z,)(pg, op1, op2);
+}
+
+svuint8_t test_svqsub_n_u8_z(svbool_t pg, svuint8_t op1, uint8_t op2)
+{
+ // CHECK-LABEL: test_svqsub_n_u8_z
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uqsub.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_n_u8_z'}}
+ return SVE_ACLE_FUNC(svqsub,_n_u8,_z,)(pg, op1, op2);
+}
+
+svuint16_t test_svqsub_n_u16_z(svbool_t pg, svuint16_t op1, uint16_t op2)
+{
+ // CHECK-LABEL: test_svqsub_n_u16_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uqsub.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_n_u16_z'}}
+ return SVE_ACLE_FUNC(svqsub,_n_u16,_z,)(pg, op1, op2);
+}
+
+svuint32_t test_svqsub_n_u32_z(svbool_t pg, svuint32_t op1, uint32_t op2)
+{
+ // CHECK-LABEL: test_svqsub_n_u32_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uqsub.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_n_u32_z'}}
+ return SVE_ACLE_FUNC(svqsub,_n_u32,_z,)(pg, op1, op2);
+}
+
+svuint64_t test_svqsub_n_u64_z(svbool_t pg, svuint64_t op1, uint64_t op2)
+{
+ // CHECK-LABEL: test_svqsub_n_u64_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uqsub.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_n_u64_z'}}
+ return SVE_ACLE_FUNC(svqsub,_n_u64,_z,)(pg, op1, op2);
+}
+
+svint8_t test_svqsub_n_s8_m(svbool_t pg, svint8_t op1, int8_t op2)
+{
+ // CHECK-LABEL: test_svqsub_n_s8_m
+ // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sqsub.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_n_s8_m'}}
+ return SVE_ACLE_FUNC(svqsub,_n_s8,_m,)(pg, op1, op2);
+}
+
+svint16_t test_svqsub_n_s16_m(svbool_t pg, svint16_t op1, int16_t op2)
+{
+ // CHECK-LABEL: test_svqsub_n_s16_m
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_n_s16_m'}}
+ return SVE_ACLE_FUNC(svqsub,_n_s16,_m,)(pg, op1, op2);
+}
+
+svint32_t test_svqsub_n_s32_m(svbool_t pg, svint32_t op1, int32_t op2)
+{
+ // CHECK-LABEL: test_svqsub_n_s32_m
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_n_s32_m'}}
+ return SVE_ACLE_FUNC(svqsub,_n_s32,_m,)(pg, op1, op2);
+}
+
+svint64_t test_svqsub_n_s64_m(svbool_t pg, svint64_t op1, int64_t op2)
+{
+ // CHECK-LABEL: test_svqsub_n_s64_m
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_n_s64_m'}}
+ return SVE_ACLE_FUNC(svqsub,_n_s64,_m,)(pg, op1, op2);
+}
+
+svuint8_t test_svqsub_n_u8_m(svbool_t pg, svuint8_t op1, uint8_t op2)
+{
+ // CHECK-LABEL: test_svqsub_n_u8_m
+ // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uqsub.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_n_u8_m'}}
+ return SVE_ACLE_FUNC(svqsub,_n_u8,_m,)(pg, op1, op2);
+}
+
+svuint16_t test_svqsub_n_u16_m(svbool_t pg, svuint16_t op1, uint16_t op2)
+{
+ // CHECK-LABEL: test_svqsub_n_u16_m
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uqsub.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_n_u16_m'}}
+ return SVE_ACLE_FUNC(svqsub,_n_u16,_m,)(pg, op1, op2);
+}
+
+svuint32_t test_svqsub_n_u32_m(svbool_t pg, svuint32_t op1, uint32_t op2)
+{
+ // CHECK-LABEL: test_svqsub_n_u32_m
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uqsub.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_n_u32_m'}}
+ return SVE_ACLE_FUNC(svqsub,_n_u32,_m,)(pg, op1, op2);
+}
+
+svuint64_t test_svqsub_n_u64_m(svbool_t pg, svuint64_t op1, uint64_t op2)
+{
+ // CHECK-LABEL: test_svqsub_n_u64_m
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uqsub.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_n_u64_m'}}
+ return SVE_ACLE_FUNC(svqsub,_n_u64,_m,)(pg, op1, op2);
+}
+
+svint8_t test_svqsub_n_s8_x(svbool_t pg, svint8_t op1, int8_t op2)
+{
+ // CHECK-LABEL: test_svqsub_n_s8_x
+ // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sqsub.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_n_s8_x'}}
+ return SVE_ACLE_FUNC(svqsub,_n_s8,_x,)(pg, op1, op2);
+}
+
+svint16_t test_svqsub_n_s16_x(svbool_t pg, svint16_t op1, int16_t op2)
+{
+ // CHECK-LABEL: test_svqsub_n_s16_x
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_n_s16_x'}}
+ return SVE_ACLE_FUNC(svqsub,_n_s16,_x,)(pg, op1, op2);
+}
+
+svint32_t test_svqsub_n_s32_x(svbool_t pg, svint32_t op1, int32_t op2)
+{
+ // CHECK-LABEL: test_svqsub_n_s32_x
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_n_s32_x'}}
+ return SVE_ACLE_FUNC(svqsub,_n_s32,_x,)(pg, op1, op2);
+}
+
+svint64_t test_svqsub_n_s64_x(svbool_t pg, svint64_t op1, int64_t op2)
+{
+ // CHECK-LABEL: test_svqsub_n_s64_x
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_n_s64_x'}}
+ return SVE_ACLE_FUNC(svqsub,_n_s64,_x,)(pg, op1, op2);
+}
+
+svuint8_t test_svqsub_n_u8_x(svbool_t pg, svuint8_t op1, uint8_t op2)
+{
+ // CHECK-LABEL: test_svqsub_n_u8_x
+ // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uqsub.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_n_u8_x'}}
+ return SVE_ACLE_FUNC(svqsub,_n_u8,_x,)(pg, op1, op2);
+}
+
+svuint16_t test_svqsub_n_u16_x(svbool_t pg, svuint16_t op1, uint16_t op2)
+{
+ // CHECK-LABEL: test_svqsub_n_u16_x
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uqsub.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_n_u16_x'}}
+ return SVE_ACLE_FUNC(svqsub,_n_u16,_x,)(pg, op1, op2);
+}
+
+svuint32_t test_svqsub_n_u32_x(svbool_t pg, svuint32_t op1, uint32_t op2)
+{
+ // CHECK-LABEL: test_svqsub_n_u32_x
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uqsub.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_n_u32_x'}}
+ return SVE_ACLE_FUNC(svqsub,_n_u32,_x,)(pg, op1, op2);
+}
+
+svuint64_t test_svqsub_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2)
+{
+ // CHECK-LABEL: test_svqsub_n_u64_x
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uqsub.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsub_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsub_n_u64_x'}}
+ return SVE_ACLE_FUNC(svqsub,_n_u64,_x,)(pg, op1, op2);
+}
diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qsubr.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qsubr.c
new file mode 100644
index 000000000000..c0146876d648
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qsubr.c
@@ -0,0 +1,569 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s
+
+#include <arm_sve.h>
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+svint8_t test_svqsubr_s8_z(svbool_t pg, svint8_t op1, svint8_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_s8_z
+ // CHECK: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sqsubr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_s8_z'}}
+ return SVE_ACLE_FUNC(svqsubr,_s8,_z,)(pg, op1, op2);
+}
+
+svint16_t test_svqsubr_s16_z(svbool_t pg, svint16_t op1, svint16_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_s16_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sqsubr.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_s16_z'}}
+ return SVE_ACLE_FUNC(svqsubr,_s16,_z,)(pg, op1, op2);
+}
+
+svint32_t test_svqsubr_s32_z(svbool_t pg, svint32_t op1, svint32_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_s32_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sqsubr.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_s32_z'}}
+ return SVE_ACLE_FUNC(svqsubr,_s32,_z,)(pg, op1, op2);
+}
+
+svint64_t test_svqsubr_s64_z(svbool_t pg, svint64_t op1, svint64_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_s64_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sqsubr.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_s64_z'}}
+ return SVE_ACLE_FUNC(svqsubr,_s64,_z,)(pg, op1, op2);
+}
+
+svuint8_t test_svqsubr_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_u8_z
+ // CHECK: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uqsubr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_u8_z'}}
+ return SVE_ACLE_FUNC(svqsubr,_u8,_z,)(pg, op1, op2);
+}
+
+svuint16_t test_svqsubr_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_u16_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uqsubr.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_u16_z'}}
+ return SVE_ACLE_FUNC(svqsubr,_u16,_z,)(pg, op1, op2);
+}
+
+svuint32_t test_svqsubr_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_u32_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uqsubr.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_u32_z'}}
+ return SVE_ACLE_FUNC(svqsubr,_u32,_z,)(pg, op1, op2);
+}
+
+svuint64_t test_svqsubr_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_u64_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uqsubr.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_u64_z'}}
+ return SVE_ACLE_FUNC(svqsubr,_u64,_z,)(pg, op1, op2);
+}
+
+svint8_t test_svqsubr_s8_m(svbool_t pg, svint8_t op1, svint8_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_s8_m
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sqsubr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_s8_m'}}
+ return SVE_ACLE_FUNC(svqsubr,_s8,_m,)(pg, op1, op2);
+}
+
+svint16_t test_svqsubr_s16_m(svbool_t pg, svint16_t op1, svint16_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_s16_m
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sqsubr.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_s16_m'}}
+ return SVE_ACLE_FUNC(svqsubr,_s16,_m,)(pg, op1, op2);
+}
+
+svint32_t test_svqsubr_s32_m(svbool_t pg, svint32_t op1, svint32_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_s32_m
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sqsubr.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_s32_m'}}
+ return SVE_ACLE_FUNC(svqsubr,_s32,_m,)(pg, op1, op2);
+}
+
+svint64_t test_svqsubr_s64_m(svbool_t pg, svint64_t op1, svint64_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_s64_m
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sqsubr.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_s64_m'}}
+ return SVE_ACLE_FUNC(svqsubr,_s64,_m,)(pg, op1, op2);
+}
+
+svuint8_t test_svqsubr_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_u8_m
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uqsubr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_u8_m'}}
+ return SVE_ACLE_FUNC(svqsubr,_u8,_m,)(pg, op1, op2);
+}
+
+svuint16_t test_svqsubr_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_u16_m
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uqsubr.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_u16_m'}}
+ return SVE_ACLE_FUNC(svqsubr,_u16,_m,)(pg, op1, op2);
+}
+
+svuint32_t test_svqsubr_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_u32_m
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uqsubr.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_u32_m'}}
+ return SVE_ACLE_FUNC(svqsubr,_u32,_m,)(pg, op1, op2);
+}
+
+svuint64_t test_svqsubr_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_u64_m
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uqsubr.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_u64_m'}}
+ return SVE_ACLE_FUNC(svqsubr,_u64,_m,)(pg, op1, op2);
+}
+
+svint8_t test_svqsubr_s8_x(svbool_t pg, svint8_t op1, svint8_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_s8_x
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sqsubr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_s8_x'}}
+ return SVE_ACLE_FUNC(svqsubr,_s8,_x,)(pg, op1, op2);
+}
+
+svint16_t test_svqsubr_s16_x(svbool_t pg, svint16_t op1, svint16_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_s16_x
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sqsubr.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_s16_x'}}
+ return SVE_ACLE_FUNC(svqsubr,_s16,_x,)(pg, op1, op2);
+}
+
+svint32_t test_svqsubr_s32_x(svbool_t pg, svint32_t op1, svint32_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_s32_x
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sqsubr.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_s32_x'}}
+ return SVE_ACLE_FUNC(svqsubr,_s32,_x,)(pg, op1, op2);
+}
+
+svint64_t test_svqsubr_s64_x(svbool_t pg, svint64_t op1, svint64_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_s64_x
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sqsubr.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_s64_x'}}
+ return SVE_ACLE_FUNC(svqsubr,_s64,_x,)(pg, op1, op2);
+}
+
+svuint8_t test_svqsubr_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_u8_x
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uqsubr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_u8_x'}}
+ return SVE_ACLE_FUNC(svqsubr,_u8,_x,)(pg, op1, op2);
+}
+
+svuint16_t test_svqsubr_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_u16_x
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uqsubr.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_u16_x'}}
+ return SVE_ACLE_FUNC(svqsubr,_u16,_x,)(pg, op1, op2);
+}
+
+svuint32_t test_svqsubr_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_u32_x
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uqsubr.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_u32_x'}}
+ return SVE_ACLE_FUNC(svqsubr,_u32,_x,)(pg, op1, op2);
+}
+
+svuint64_t test_svqsubr_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_u64_x
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uqsubr.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_u64_x'}}
+ return SVE_ACLE_FUNC(svqsubr,_u64,_x,)(pg, op1, op2);
+}
+
+svint8_t test_svqsubr_n_s8_z(svbool_t pg, svint8_t op1, int8_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_n_s8_z
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sqsubr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_n_s8_z'}}
+ return SVE_ACLE_FUNC(svqsubr,_n_s8,_z,)(pg, op1, op2);
+}
+
+svint16_t test_svqsubr_n_s16_z(svbool_t pg, svint16_t op1, int16_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_n_s16_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sqsubr.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_n_s16_z'}}
+ return SVE_ACLE_FUNC(svqsubr,_n_s16,_z,)(pg, op1, op2);
+}
+
+svint32_t test_svqsubr_n_s32_z(svbool_t pg, svint32_t op1, int32_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_n_s32_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sqsubr.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_n_s32_z'}}
+ return SVE_ACLE_FUNC(svqsubr,_n_s32,_z,)(pg, op1, op2);
+}
+
+svint64_t test_svqsubr_n_s64_z(svbool_t pg, svint64_t op1, int64_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_n_s64_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sqsubr.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_n_s64_z'}}
+ return SVE_ACLE_FUNC(svqsubr,_n_s64,_z,)(pg, op1, op2);
+}
+
+svuint8_t test_svqsubr_n_u8_z(svbool_t pg, svuint8_t op1, uint8_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_n_u8_z
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uqsubr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_n_u8_z'}}
+ return SVE_ACLE_FUNC(svqsubr,_n_u8,_z,)(pg, op1, op2);
+}
+
+svuint16_t test_svqsubr_n_u16_z(svbool_t pg, svuint16_t op1, uint16_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_n_u16_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uqsubr.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_n_u16_z'}}
+ return SVE_ACLE_FUNC(svqsubr,_n_u16,_z,)(pg, op1, op2);
+}
+
+svuint32_t test_svqsubr_n_u32_z(svbool_t pg, svuint32_t op1, uint32_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_n_u32_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uqsubr.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_n_u32_z'}}
+ return SVE_ACLE_FUNC(svqsubr,_n_u32,_z,)(pg, op1, op2);
+}
+
+svuint64_t test_svqsubr_n_u64_z(svbool_t pg, svuint64_t op1, uint64_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_n_u64_z
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uqsubr.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_n_u64_z'}}
+ return SVE_ACLE_FUNC(svqsubr,_n_u64,_z,)(pg, op1, op2);
+}
+
+svint8_t test_svqsubr_n_s8_m(svbool_t pg, svint8_t op1, int8_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_n_s8_m
+ // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sqsubr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_n_s8_m'}}
+ return SVE_ACLE_FUNC(svqsubr,_n_s8,_m,)(pg, op1, op2);
+}
+
+svint16_t test_svqsubr_n_s16_m(svbool_t pg, svint16_t op1, int16_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_n_s16_m
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sqsubr.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_n_s16_m'}}
+ return SVE_ACLE_FUNC(svqsubr,_n_s16,_m,)(pg, op1, op2);
+}
+
+svint32_t test_svqsubr_n_s32_m(svbool_t pg, svint32_t op1, int32_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_n_s32_m
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sqsubr.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_n_s32_m'}}
+ return SVE_ACLE_FUNC(svqsubr,_n_s32,_m,)(pg, op1, op2);
+}
+
+svint64_t test_svqsubr_n_s64_m(svbool_t pg, svint64_t op1, int64_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_n_s64_m
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sqsubr.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_n_s64_m'}}
+ return SVE_ACLE_FUNC(svqsubr,_n_s64,_m,)(pg, op1, op2);
+}
+
+svuint8_t test_svqsubr_n_u8_m(svbool_t pg, svuint8_t op1, uint8_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_n_u8_m
+ // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uqsubr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_n_u8_m'}}
+ return SVE_ACLE_FUNC(svqsubr,_n_u8,_m,)(pg, op1, op2);
+}
+
+svuint16_t test_svqsubr_n_u16_m(svbool_t pg, svuint16_t op1, uint16_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_n_u16_m
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uqsubr.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_n_u16_m'}}
+ return SVE_ACLE_FUNC(svqsubr,_n_u16,_m,)(pg, op1, op2);
+}
+
+svuint32_t test_svqsubr_n_u32_m(svbool_t pg, svuint32_t op1, uint32_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_n_u32_m
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uqsubr.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_n_u32_m'}}
+ return SVE_ACLE_FUNC(svqsubr,_n_u32,_m,)(pg, op1, op2);
+}
+
+svuint64_t test_svqsubr_n_u64_m(svbool_t pg, svuint64_t op1, uint64_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_n_u64_m
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uqsubr.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_n_u64_m'}}
+ return SVE_ACLE_FUNC(svqsubr,_n_u64,_m,)(pg, op1, op2);
+}
+
+svint8_t test_svqsubr_n_s8_x(svbool_t pg, svint8_t op1, int8_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_n_s8_x
+ // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sqsubr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_n_s8_x'}}
+ return SVE_ACLE_FUNC(svqsubr,_n_s8,_x,)(pg, op1, op2);
+}
+
+svint16_t test_svqsubr_n_s16_x(svbool_t pg, svint16_t op1, int16_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_n_s16_x
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sqsubr.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_n_s16_x'}}
+ return SVE_ACLE_FUNC(svqsubr,_n_s16,_x,)(pg, op1, op2);
+}
+
+svint32_t test_svqsubr_n_s32_x(svbool_t pg, svint32_t op1, int32_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_n_s32_x
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sqsubr.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_n_s32_x'}}
+ return SVE_ACLE_FUNC(svqsubr,_n_s32,_x,)(pg, op1, op2);
+}
+
+svint64_t test_svqsubr_n_s64_x(svbool_t pg, svint64_t op1, int64_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_n_s64_x
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sqsubr.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_n_s64_x'}}
+ return SVE_ACLE_FUNC(svqsubr,_n_s64,_x,)(pg, op1, op2);
+}
+
+svuint8_t test_svqsubr_n_u8_x(svbool_t pg, svuint8_t op1, uint8_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_n_u8_x
+ // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.uqsubr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_n_u8_x'}}
+ return SVE_ACLE_FUNC(svqsubr,_n_u8,_x,)(pg, op1, op2);
+}
+
+svuint16_t test_svqsubr_n_u16_x(svbool_t pg, svuint16_t op1, uint16_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_n_u16_x
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uqsubr.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_n_u16_x'}}
+ return SVE_ACLE_FUNC(svqsubr,_n_u16,_x,)(pg, op1, op2);
+}
+
+svuint32_t test_svqsubr_n_u32_x(svbool_t pg, svuint32_t op1, uint32_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_n_u32_x
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uqsubr.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_n_u32_x'}}
+ return SVE_ACLE_FUNC(svqsubr,_n_u32,_x,)(pg, op1, op2);
+}
+
+svuint64_t test_svqsubr_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2)
+{
+ // CHECK-LABEL: test_svqsubr_n_u64_x
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uqsubr.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svqsubr_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svqsubr_n_u64_x'}}
+ return SVE_ACLE_FUNC(svqsubr,_n_u64,_x,)(pg, op1, op2);
+}
diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_recpe.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_recpe.c
new file mode 100644
index 000000000000..7f9c804746c1
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_recpe.c
@@ -0,0 +1,46 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s
+
+#include <arm_sve.h>
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+svuint32_t test_svrecpe_u32_z(svbool_t pg, svuint32_t op)
+{
+ // CHECK-LABEL: test_svrecpe_u32_z
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.urecpe.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrecpe_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrecpe_u32_z'}}
+ return SVE_ACLE_FUNC(svrecpe,_u32,_z,)(pg, op);
+}
+
+svuint32_t test_svrecpe_u32_m(svuint32_t inactive, svbool_t pg, svuint32_t op)
+{
+ // CHECK-LABEL: test_svrecpe_u32_m
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.urecpe.nxv4i32(<vscale x 4 x i32> %inactive, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrecpe_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrecpe_u32_m'}}
+ return SVE_ACLE_FUNC(svrecpe,_u32,_m,)(inactive, pg, op);
+}
+
+svuint32_t test_svrecpe_u32_x(svbool_t pg, svuint32_t op)
+{
+ // CHECK-LABEL: test_svrecpe_u32_x
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.urecpe.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrecpe_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrecpe_u32_x'}}
+ return SVE_ACLE_FUNC(svrecpe,_u32,_x,)(pg, op);
+}
diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rhadd.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rhadd.c
new file mode 100644
index 000000000000..e3731e521568
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rhadd.c
@@ -0,0 +1,568 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s
+#include <arm_sve.h>
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+svint8_t test_svrhadd_s8_m(svbool_t pg, svint8_t op1, svint8_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_s8_m
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.srhadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_s8_m'}}
+ return SVE_ACLE_FUNC(svrhadd,_s8,_m,)(pg, op1, op2);
+}
+
+svint16_t test_svrhadd_s16_m(svbool_t pg, svint16_t op1, svint16_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_s16_m
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.srhadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_s16_m'}}
+ return SVE_ACLE_FUNC(svrhadd,_s16,_m,)(pg, op1, op2);
+}
+
+svint32_t test_svrhadd_s32_m(svbool_t pg, svint32_t op1, svint32_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_s32_m
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.srhadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_s32_m'}}
+ return SVE_ACLE_FUNC(svrhadd,_s32,_m,)(pg, op1, op2);
+}
+
+svint64_t test_svrhadd_s64_m(svbool_t pg, svint64_t op1, svint64_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_s64_m
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.srhadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_s64_m'}}
+ return SVE_ACLE_FUNC(svrhadd,_s64,_m,)(pg, op1, op2);
+}
+
+svuint8_t test_svrhadd_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_u8_m
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.urhadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_u8_m'}}
+ return SVE_ACLE_FUNC(svrhadd,_u8,_m,)(pg, op1, op2);
+}
+
+svuint16_t test_svrhadd_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_u16_m
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.urhadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_u16_m'}}
+ return SVE_ACLE_FUNC(svrhadd,_u16,_m,)(pg, op1, op2);
+}
+
+svuint32_t test_svrhadd_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2)
+{
+ // CHECKA-LABEL: test_svrhadd_u32_m
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.urhadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_u32_m'}}
+ return SVE_ACLE_FUNC(svrhadd,_u32,_m,)(pg, op1, op2);
+}
+
+svuint64_t test_svrhadd_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_u64_m
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.urhadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_u64_m'}}
+ return SVE_ACLE_FUNC(svrhadd,_u64,_m,)(pg, op1, op2);
+}
+
+svint8_t test_svrhadd_n_s8_m(svbool_t pg, svint8_t op1, int8_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_n_s8_m
+ // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.srhadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_n_s8_m'}}
+ return SVE_ACLE_FUNC(svrhadd,_n_s8,_m,)(pg, op1, op2);
+}
+
+svint16_t test_svrhadd_n_s16_m(svbool_t pg, svint16_t op1, int16_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_n_s16_m
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.srhadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_n_s16_m'}}
+ return SVE_ACLE_FUNC(svrhadd,_n_s16,_m,)(pg, op1, op2);
+}
+
+svint32_t test_svrhadd_n_s32_m(svbool_t pg, svint32_t op1, int32_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_n_s32_m
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.srhadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_n_s32_m'}}
+ return SVE_ACLE_FUNC(svrhadd,_n_s32,_m,)(pg, op1, op2);
+}
+
+svint64_t test_svrhadd_n_s64_m(svbool_t pg, svint64_t op1, int64_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_n_s64_m
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.srhadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_n_s64_m'}}
+ return SVE_ACLE_FUNC(svrhadd,_n_s64,_m,)(pg, op1, op2);
+}
+
+svuint8_t test_svrhadd_n_u8_m(svbool_t pg, svuint8_t op1, uint8_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_n_u8_m
+ // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.urhadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_n_u8_m'}}
+ return SVE_ACLE_FUNC(svrhadd,_n_u8,_m,)(pg, op1, op2);
+}
+
+svuint16_t test_svrhadd_n_u16_m(svbool_t pg, svuint16_t op1, uint16_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_n_u16_m
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.urhadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_n_u16_m'}}
+ return SVE_ACLE_FUNC(svrhadd,_n_u16,_m,)(pg, op1, op2);
+}
+
+svuint32_t test_svrhadd_n_u32_m(svbool_t pg, svuint32_t op1, uint32_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_n_u32_m
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.urhadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_n_u32_m'}}
+ return SVE_ACLE_FUNC(svrhadd,_n_u32,_m,)(pg, op1, op2);
+}
+
+svuint64_t test_svrhadd_n_u64_m(svbool_t pg, svuint64_t op1, uint64_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_n_u64_m
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.urhadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_n_u64_m'}}
+ return SVE_ACLE_FUNC(svrhadd,_n_u64,_m,)(pg, op1, op2);
+}
+
+svint8_t test_svrhadd_s8_z(svbool_t pg, svint8_t op1, svint8_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_s8_z
+ // CHECK: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.srhadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_s8_z'}}
+ return SVE_ACLE_FUNC(svrhadd,_s8,_z,)(pg, op1, op2);
+}
+
+svint16_t test_svrhadd_s16_z(svbool_t pg, svint16_t op1, svint16_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_s16_z
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.srhadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_s16_z'}}
+ return SVE_ACLE_FUNC(svrhadd,_s16,_z,)(pg, op1, op2);
+}
+
+svint32_t test_svrhadd_s32_z(svbool_t pg, svint32_t op1, svint32_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_s32_z
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.srhadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_s32_z'}}
+ return SVE_ACLE_FUNC(svrhadd,_s32,_z,)(pg, op1, op2);
+}
+
+svint64_t test_svrhadd_s64_z(svbool_t pg, svint64_t op1, svint64_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_s64_z
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.srhadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_s64_z'}}
+ return SVE_ACLE_FUNC(svrhadd,_s64,_z,)(pg, op1, op2);
+}
+
+svuint8_t test_svrhadd_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_u8_z
+ // CHECK: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.urhadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_u8_z'}}
+ return SVE_ACLE_FUNC(svrhadd,_u8,_z,)(pg, op1, op2);
+}
+
+svuint16_t test_svrhadd_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_u16_z
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.urhadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_u16_z'}}
+ return SVE_ACLE_FUNC(svrhadd,_u16,_z,)(pg, op1, op2);
+}
+
+svuint32_t test_svrhadd_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2)
+{
+ // CHECKA-LABEL: test_svrhadd_u32_z
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.urhadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_u32_z'}}
+ return SVE_ACLE_FUNC(svrhadd,_u32,_z,)(pg, op1, op2);
+}
+
+svuint64_t test_svrhadd_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_u64_z
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.urhadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_u64_z'}}
+ return SVE_ACLE_FUNC(svrhadd,_u64,_z,)(pg, op1, op2);
+}
+
+svint8_t test_svrhadd_n_s8_z(svbool_t pg, svint8_t op1, int8_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_n_s8_z
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.srhadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_n_s8_z'}}
+ return SVE_ACLE_FUNC(svrhadd,_n_s8,_z,)(pg, op1, op2);
+}
+
+svint16_t test_svrhadd_n_s16_z(svbool_t pg, svint16_t op1, int16_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_n_s16_z
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.srhadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_n_s16_z'}}
+ return SVE_ACLE_FUNC(svrhadd,_n_s16,_z,)(pg, op1, op2);
+}
+
+svint32_t test_svrhadd_n_s32_z(svbool_t pg, svint32_t op1, int32_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_n_s32_z
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.srhadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_n_s32_z'}}
+ return SVE_ACLE_FUNC(svrhadd,_n_s32,_z,)(pg, op1, op2);
+}
+
+svint64_t test_svrhadd_n_s64_z(svbool_t pg, svint64_t op1, int64_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_n_s64_z
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.srhadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_n_s64_z'}}
+ return SVE_ACLE_FUNC(svrhadd,_n_s64,_z,)(pg, op1, op2);
+}
+
+svuint8_t test_svrhadd_n_u8_z(svbool_t pg, svuint8_t op1, uint8_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_n_u8_z
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.urhadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_n_u8_z'}}
+ return SVE_ACLE_FUNC(svrhadd,_n_u8,_z,)(pg, op1, op2);
+}
+
+svuint16_t test_svrhadd_n_u16_z(svbool_t pg, svuint16_t op1, uint16_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_n_u16_z
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.urhadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_n_u16_z'}}
+ return SVE_ACLE_FUNC(svrhadd,_n_u16,_z,)(pg, op1, op2);
+}
+
+svuint32_t test_svrhadd_n_u32_z(svbool_t pg, svuint32_t op1, uint32_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_n_u32_z
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.urhadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_n_u32_z'}}
+ return SVE_ACLE_FUNC(svrhadd,_n_u32,_z,)(pg, op1, op2);
+}
+
+svuint64_t test_svrhadd_n_u64_z(svbool_t pg, svuint64_t op1, uint64_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_n_u64_z
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.urhadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_n_u64_z'}}
+ return SVE_ACLE_FUNC(svrhadd,_n_u64,_z,)(pg, op1, op2);
+}
+
+svint8_t test_svrhadd_s8_x(svbool_t pg, svint8_t op1, svint8_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_s8_x
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.srhadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_s8_x'}}
+ return SVE_ACLE_FUNC(svrhadd,_s8,_x,)(pg, op1, op2);
+}
+
+svint16_t test_svrhadd_s16_x(svbool_t pg, svint16_t op1, svint16_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_s16_x
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.srhadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_s16_x'}}
+ return SVE_ACLE_FUNC(svrhadd,_s16,_x,)(pg, op1, op2);
+}
+
+svint32_t test_svrhadd_s32_x(svbool_t pg, svint32_t op1, svint32_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_s32_x
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.srhadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_s32_x'}}
+ return SVE_ACLE_FUNC(svrhadd,_s32,_x,)(pg, op1, op2);
+}
+
+svint64_t test_svrhadd_s64_x(svbool_t pg, svint64_t op1, svint64_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_s64_x
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.srhadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_s64_x'}}
+ return SVE_ACLE_FUNC(svrhadd,_s64,_x,)(pg, op1, op2);
+}
+
+svuint8_t test_svrhadd_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_u8_x
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.urhadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2)
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_u8_x'}}
+ return SVE_ACLE_FUNC(svrhadd,_u8,_x,)(pg, op1, op2);
+}
+
+svuint16_t test_svrhadd_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_u16_x
+ // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.urhadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2)
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_u16_x'}}
+ return SVE_ACLE_FUNC(svrhadd,_u16,_x,)(pg, op1, op2);
+}
+
+svuint32_t test_svrhadd_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2)
+{
+ // CHECKA-LABEL: test_svrhadd_u32_x
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.urhadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_u32_x'}}
+ return SVE_ACLE_FUNC(svrhadd,_u32,_x,)(pg, op1, op2);
+}
+
+svuint64_t test_svrhadd_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_u64_x
+ // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.urhadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2)
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_u64_x'}}
+ return SVE_ACLE_FUNC(svrhadd,_u64,_x,)(pg, op1, op2);
+}
+
+svint8_t test_svrhadd_n_s8_x(svbool_t pg, svint8_t op1, int8_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_n_s8_x
+ // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.srhadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_n_s8_x'}}
+ return SVE_ACLE_FUNC(svrhadd,_n_s8,_x,)(pg, op1, op2);
+}
+
+svint16_t test_svrhadd_n_s16_x(svbool_t pg, svint16_t op1, int16_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_n_s16_x
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.srhadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_n_s16_x'}}
+ return SVE_ACLE_FUNC(svrhadd,_n_s16,_x,)(pg, op1, op2);
+}
+
+svint32_t test_svrhadd_n_s32_x(svbool_t pg, svint32_t op1, int32_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_n_s32_x
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.srhadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_n_s32_x'}}
+ return SVE_ACLE_FUNC(svrhadd,_n_s32,_x,)(pg, op1, op2);
+}
+
+svint64_t test_svrhadd_n_s64_x(svbool_t pg, svint64_t op1, int64_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_n_s64_x
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.srhadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_n_s64_x'}}
+ return SVE_ACLE_FUNC(svrhadd,_n_s64,_x,)(pg, op1, op2);
+}
+
+svuint8_t test_svrhadd_n_u8_x(svbool_t pg, svuint8_t op1, uint8_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_n_u8_x
+ // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op2)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.urhadd.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %[[DUP]])
+ // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_n_u8_x'}}
+ return SVE_ACLE_FUNC(svrhadd,_n_u8,_x,)(pg, op1, op2);
+}
+
+svuint16_t test_svrhadd_n_u16_x(svbool_t pg, svuint16_t op1, uint16_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_n_u16_x
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.urhadd.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %[[DUP]])
+ // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_n_u16_x'}}
+ return SVE_ACLE_FUNC(svrhadd,_n_u16,_x,)(pg, op1, op2);
+}
+
+svuint32_t test_svrhadd_n_u32_x(svbool_t pg, svuint32_t op1, uint32_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_n_u32_x
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.urhadd.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %[[DUP]])
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_n_u32_x'}}
+ return SVE_ACLE_FUNC(svrhadd,_n_u32,_x,)(pg, op1, op2);
+}
+
+svuint64_t test_svrhadd_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2)
+{
+ // CHECK-LABEL: test_svrhadd_n_u64_x
+ // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op2)
+ // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.urhadd.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %[[DUP]])
+ // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrhadd_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrhadd_n_u64_x'}}
+ return SVE_ACLE_FUNC(svrhadd,_n_u64,_x,)(pg, op1, op2);
+}
diff --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rsqrte.c b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rsqrte.c
new file mode 100644
index 000000000000..02fb5f61e9d2
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rsqrte.c
@@ -0,0 +1,46 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s
+
+#include <arm_sve.h>
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+svuint32_t test_svrsqrte_u32_z(svbool_t pg, svuint32_t op)
+{
+ // CHECK-LABEL: test_svrsqrte_u32_z
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.ursqrte.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrsqrte_z'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrsqrte_u32_z'}}
+ return SVE_ACLE_FUNC(svrsqrte,_u32,_z,)(pg, op);
+}
+
+svuint32_t test_svrsqrte_u32_m(svuint32_t inactive, svbool_t pg, svuint32_t op)
+{
+ // CHECK-LABEL: test_svrsqrte_u32_m
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.ursqrte.nxv4i32(<vscale x 4 x i32> %inactive, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrsqrte_m'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrsqrte_u32_m'}}
+ return SVE_ACLE_FUNC(svrsqrte,_u32,_m,)(inactive, pg, op);
+}
+
+svuint32_t test_svrsqrte_u32_x(svbool_t pg, svuint32_t op)
+{
+ // CHECK-LABEL: test_svrsqrte_u32_x
+ // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
+ // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.ursqrte.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op)
+ // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
+ // overload-warning at +2 {{implicit declaration of function 'svrsqrte_x'}}
+ // expected-warning at +1 {{implicit declaration of function 'svrsqrte_u32_x'}}
+ return SVE_ACLE_FUNC(svrsqrte,_u32,_x,)(pg, op);
+}
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