[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

[James Clarke via Phabricator via cfe-commits]

jrtc27 added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/reserved-regs.ll:71
+
+; X1-NOT: lw ra,
+; X1-NOT: ld ra,
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lenary wrote:
> These tests aren't going to test what you think they are, or at least aren't going to fail when you hope they are, as the allocator will probably choose a0 for these registers, even if other registers are available (it uses the GPRs in a specific order, starting with the first free one, which will usually be a0).
This is approximately what `llvm/test/CodeGen/AArch64/arm64-platform-reg.ll` is doing, and the pint is that `@var` is big enough that the register allocator will use every register it can so the order shouldn't matter.

As for reserving registers that have a specific use in the calling convention, AArch64 allows you to use them but won't let you make function calls (`llvm/test/CodeGen/AArch64/arm64-reserved-arg-reg-call-error.ll`). I don't know what it does about function arguments though, it probably assumes they're in the ABI registers on entry but then doesn't allocate/clobber those registers within the function? I'm not quite sure what that's useful for though. GCC has this to say about the flag:

> Treat the register named reg as a fixed register; generated code should never refer to it (except perhaps as a stack pointer, frame pointer or in some other fixed role).

So it's pretty vague about what can happen if you try and reserve a register normally used for other things...


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  https://reviews.llvm.org/D67185/new/

https://reviews.llvm.org/D67185