[PATCH] D66822: Hardware cache line size builtins

[Roman Lebedev via Phabricator via cfe-commits]

lebedev.ri added a comment.

> My implementation switches on the target triple to get the max cache line size for that target. I am not sure if this is the best way to implement these builtins, but it will ensure that there is not an ABI break.

Passing-by remark: i'm not sure it is possible to **guarantee** that this will be always correct and that no ABI break will happen.
What if some next model of e.g. x86 processor has 128-byte-wide cache line?
You nominally can't bump the value because it will be an ABI break,
but the default is no longer conservatively correct there - it is smaller than needed,
which will effectively cripple all usages where this size is used as an alignment to avoid cache line sharing.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D66822/new/

https://reviews.llvm.org/D66822